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drm/msm: add MSM_BO_CACHED_COHERENT
Add a new cache mode for creating coherent host-cached BOs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Link: https://lore.kernel.org/r/20210423190833.25319-5-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
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@ -466,6 +466,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
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config.rev.minor, config.rev.patchid);
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config.rev.minor, config.rev.patchid);
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priv->is_a2xx = config.rev.core == 2;
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priv->is_a2xx = config.rev.core == 2;
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priv->has_cached_coherent = config.rev.core >= 6;
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gpu = info->init(drm);
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gpu = info->init(drm);
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if (IS_ERR(gpu)) {
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if (IS_ERR(gpu)) {
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@ -41,9 +41,10 @@
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* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
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* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
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* - 1.6.0 - Syncobj support
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* - 1.6.0 - Syncobj support
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* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
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* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
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* - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
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*/
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*/
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#define MSM_VERSION_MAJOR 1
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#define MSM_VERSION_MAJOR 1
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#define MSM_VERSION_MINOR 7
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#define MSM_VERSION_MINOR 8
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#define MSM_VERSION_PATCHLEVEL 0
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#define MSM_VERSION_PATCHLEVEL 0
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static const struct drm_mode_config_funcs mode_config_funcs = {
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static const struct drm_mode_config_funcs mode_config_funcs = {
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@ -167,6 +167,7 @@ struct msm_drm_private {
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struct msm_file_private *lastctx;
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struct msm_file_private *lastctx;
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/* gpu is only set on open(), but we need this info earlier */
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/* gpu is only set on open(), but we need this info earlier */
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bool is_a2xx;
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bool is_a2xx;
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bool has_cached_coherent;
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struct drm_fb_helper *fbdev;
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struct drm_fb_helper *fbdev;
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@ -445,6 +445,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj,
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if (msm_obj->flags & MSM_BO_MAP_PRIV)
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if (msm_obj->flags & MSM_BO_MAP_PRIV)
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prot |= IOMMU_PRIV;
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prot |= IOMMU_PRIV;
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if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
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prot |= IOMMU_CACHE;
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GEM_WARN_ON(!msm_gem_is_locked(obj));
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GEM_WARN_ON(!msm_gem_is_locked(obj));
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if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
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if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
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@ -1158,6 +1161,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
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uint32_t size, uint32_t flags,
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uint32_t size, uint32_t flags,
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struct drm_gem_object **obj)
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struct drm_gem_object **obj)
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{
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_gem_object *msm_obj;
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struct msm_gem_object *msm_obj;
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switch (flags & MSM_BO_CACHE_MASK) {
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switch (flags & MSM_BO_CACHE_MASK) {
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@ -1165,6 +1169,10 @@ static int msm_gem_new_impl(struct drm_device *dev,
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case MSM_BO_CACHED:
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case MSM_BO_CACHED:
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case MSM_BO_WC:
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case MSM_BO_WC:
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break;
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break;
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case MSM_BO_CACHED_COHERENT:
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if (priv->has_cached_coherent)
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break;
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/* fallthrough */
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default:
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default:
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DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
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DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
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(flags & MSM_BO_CACHE_MASK));
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(flags & MSM_BO_CACHE_MASK));
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@ -95,12 +95,11 @@ struct drm_msm_param {
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_UNCACHED 0x00040000
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#define MSM_BO_UNCACHED 0x00040000
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#define MSM_BO_CACHED_COHERENT 0x080000
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#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
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#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
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MSM_BO_GPU_READONLY | \
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MSM_BO_GPU_READONLY | \
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MSM_BO_CACHED | \
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MSM_BO_CACHE_MASK)
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MSM_BO_WC | \
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MSM_BO_UNCACHED)
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struct drm_msm_gem_new {
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struct drm_msm_gem_new {
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__u64 size; /* in */
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__u64 size; /* in */
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