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dt-bindings: iommu: Convert QCOM IOMMU to YAML
Convert the Qualcomm IOMMU bindings to YAML. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230406-topic-qciommu-v3-1-aa0e4f018191@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
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Konrad Dybcio
Rob Herring
parent
a0108409c7
commit
d1115de6af
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* QCOM IOMMU v1 Implementation
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Qualcomm "B" family devices which are not compatible with arm-smmu have
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a similar looking IOMMU but without access to the global register space,
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and optionally requiring additional configuration to route context irqs
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to non-secure vs secure interrupt line.
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** Required properties:
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- compatible : Should be one of:
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"qcom,msm8916-iommu"
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"qcom,msm8953-iommu"
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Followed by "qcom,msm-iommu-v1".
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- clock-names : Should be a pair of "iface" (required for IOMMUs
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register group access) and "bus" (required for
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the IOMMUs underlying bus access).
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- clocks : Phandles for respective clocks described by
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clock-names.
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- #address-cells : must be 1.
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- #size-cells : must be 1.
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- #iommu-cells : Must be 1. Index identifies the context-bank #.
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- ranges : Base address and size of the iommu context banks.
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- qcom,iommu-secure-id : secure-id.
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- List of sub-nodes, one per translation context bank. Each sub-node
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has the following required properties:
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- compatible : Should be one of:
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- "qcom,msm-iommu-v1-ns" : non-secure context bank
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- "qcom,msm-iommu-v1-sec" : secure context bank
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- reg : Base address and size of context bank within the iommu
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- interrupts : The context fault irq.
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** Optional properties:
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- reg : Base address and size of the SMMU local base, should
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be only specified if the iommu requires configuration
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for routing of context bank irq's to secure vs non-
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secure lines. (Ie. if the iommu contains secure
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context banks)
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** Examples:
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apps_iommu: iommu@1e20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#iommu-cells = <1>;
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compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
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ranges = <0 0x1e20000 0x40000>;
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reg = <0x1ef0000 0x3000>;
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clocks = <&gcc GCC_SMMU_CFG_CLK>,
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<&gcc GCC_APSS_TCU_CLK>;
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clock-names = "iface", "bus";
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qcom,iommu-secure-id = <17>;
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// mdp_0:
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iommu-ctx@4000 {
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compatible = "qcom,msm-iommu-v1-ns";
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reg = <0x4000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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};
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// venus_ns:
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iommu-ctx@5000 {
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compatible = "qcom,msm-iommu-v1-sec";
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reg = <0x5000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpu_iommu: iommu@1f08000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#iommu-cells = <1>;
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compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
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ranges = <0 0x1f08000 0x10000>;
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clocks = <&gcc GCC_SMMU_CFG_CLK>,
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<&gcc GCC_GFX_TCU_CLK>;
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clock-names = "iface", "bus";
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qcom,iommu-secure-id = <18>;
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// gfx3d_user:
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iommu-ctx@1000 {
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compatible = "qcom,msm-iommu-v1-ns";
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reg = <0x1000 0x1000>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
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};
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// gfx3d_priv:
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iommu-ctx@2000 {
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compatible = "qcom,msm-iommu-v1-ns";
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reg = <0x2000 0x1000>;
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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...
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venus: video-codec@1d00000 {
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...
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iommus = <&apps_iommu 5>;
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};
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mdp: mdp@1a01000 {
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...
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iommus = <&apps_iommu 4>;
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};
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gpu@1c00000 {
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...
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iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
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};
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113
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
Normal file
113
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
Normal file
@ -0,0 +1,113 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies legacy IOMMU implementations
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maintainers:
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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Qualcomm "B" family devices which are not compatible with arm-smmu have
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a similar looking IOMMU, but without access to the global register space
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and optionally requiring additional configuration to route context IRQs
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to non-secure vs secure interrupt line.
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8916-iommu
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- qcom,msm8953-iommu
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- const: qcom,msm-iommu-v1
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clocks:
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items:
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- description: Clock required for IOMMU register group access
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- description: Clock required for underlying bus access
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clock-names:
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items:
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- const: iface
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- const: bus
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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ranges: true
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qcom,iommu-secure-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The SCM secure ID of the IOMMU instance.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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'#iommu-cells':
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const: 1
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patternProperties:
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"^iommu-ctx@[0-9a-f]+$":
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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- qcom,msm-iommu-v1-ns
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- qcom,msm-iommu-v1-sec
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- interrupts
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- reg
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required:
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- compatible
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- clocks
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- clock-names
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- ranges
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- '#address-cells'
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- '#size-cells'
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- '#iommu-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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apps_iommu: iommu@1e20000 {
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compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
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reg = <0x01ef0000 0x3000>;
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clocks = <&gcc GCC_SMMU_CFG_CLK>,
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<&gcc GCC_APSS_TCU_CLK>;
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clock-names = "iface", "bus";
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qcom,iommu-secure-id = <17>;
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#address-cells = <1>;
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#size-cells = <1>;
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#iommu-cells = <1>;
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ranges = <0 0x01e20000 0x40000>;
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/* mdp_0: */
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iommu-ctx@4000 {
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compatible = "qcom,msm-iommu-v1-ns";
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reg = <0x4000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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