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Merge branch 'w83977af_ir-neatening'
Joe Perches says: ==================== irda: w83977af_ir: Neatening Originally on top of Arnd's overly long udelay patches because I noticed a misindented block. That's now already fixed along with some other whitespace problems. These patches are the remainder style issues from my original series. Even though I haven't turned on the netwinder in a box in the garage in who knows how long, if this device is still used somewhere, might as well neaten the code too. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
d10d019870
@ -39,6 +39,8 @@
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*
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********************************************************************/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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@ -84,13 +86,13 @@ static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
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/* Some prototypes */
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static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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unsigned int dma);
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unsigned int dma);
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static int w83977af_close(struct w83977af_ir *self);
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static int w83977af_probe(int iobase, int irq, int dma);
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static int w83977af_dma_receive(struct w83977af_ir *self);
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static int w83977af_dma_receive_complete(struct w83977af_ir *self);
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static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
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struct net_device *dev);
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struct net_device *dev);
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static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
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static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
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static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed);
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@ -110,7 +112,7 @@ static int __init w83977af_init(void)
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{
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int i;
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for (i=0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
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for (i = 0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
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if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
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return 0;
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}
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@ -127,7 +129,7 @@ static void __exit w83977af_cleanup(void)
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{
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int i;
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for (i=0; i < ARRAY_SIZE(dev_self); i++) {
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for (i = 0; i < ARRAY_SIZE(dev_self); i++) {
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if (dev_self[i])
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w83977af_close(dev_self[i]);
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}
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@ -155,8 +157,8 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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/* Lock the port that we need */
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if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
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pr_debug("%s(), can't get iobase of 0x%03x\n",
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__func__ , iobase);
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pr_debug("%s: can't get iobase of 0x%03x\n",
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__func__, iobase);
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return -ENODEV;
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}
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@ -168,9 +170,8 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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* Allocate new instance of the driver
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*/
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dev = alloc_irdadev(sizeof(struct w83977af_ir));
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if (dev == NULL) {
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printk( KERN_ERR "IrDA: Can't allocate memory for "
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"IrDA control block!\n");
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if (!dev) {
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pr_err("IrDA: Can't allocate memory for IrDA control block!\n");
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err = -ENOMEM;
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goto err_out;
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}
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@ -178,7 +179,6 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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self = netdev_priv(dev);
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spin_lock_init(&self->lock);
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/* Initialize IO */
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self->io.fir_base = iobase;
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self->io.irq = irq;
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@ -192,8 +192,8 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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/* The only value we must override it the baudrate */
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/* FIXME: The HP HDLS-1100 does not support 1152000! */
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self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
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IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
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self->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 | IR_57600 |
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IR_115200 | IR_576000 | IR_1152000 | (IR_4000000 << 8);
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/* The HP HDLS-1100 needs 1 ms according to the specs */
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self->qos.min_turn_time.bits = qos_mtt_bits;
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@ -207,7 +207,7 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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self->rx_buff.head =
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dma_zalloc_coherent(NULL, self->rx_buff.truesize,
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&self->rx_buff_dma, GFP_KERNEL);
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if (self->rx_buff.head == NULL) {
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if (!self->rx_buff.head) {
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err = -ENOMEM;
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goto err_out1;
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}
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@ -215,7 +215,7 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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self->tx_buff.head =
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dma_zalloc_coherent(NULL, self->tx_buff.truesize,
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&self->tx_buff_dma, GFP_KERNEL);
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if (self->tx_buff.head == NULL) {
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if (!self->tx_buff.head) {
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err = -ENOMEM;
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goto err_out2;
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}
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@ -230,7 +230,7 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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err = register_netdev(dev);
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if (err) {
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net_err_ratelimited("%s(), register_netdevice() failed!\n",
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net_err_ratelimited("%s:, register_netdevice() failed!\n",
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__func__);
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goto err_out3;
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}
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@ -263,7 +263,7 @@ static int w83977af_close(struct w83977af_ir *self)
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{
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int iobase;
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iobase = self->io.fir_base;
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iobase = self->io.fir_base;
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#ifdef CONFIG_USE_W977_PNP
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/* enter PnP configuration mode */
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@ -281,8 +281,7 @@ static int w83977af_close(struct w83977af_ir *self)
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unregister_netdev(self->netdev);
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/* Release the PORT that this driver is using */
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pr_debug("%s(), Releasing Region %03x\n",
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__func__ , self->io.fir_base);
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pr_debug("%s: Releasing Region %03x\n", __func__, self->io.fir_base);
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release_region(self->io.fir_base, self->io.fir_ext);
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if (self->tx_buff.head)
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@ -303,7 +302,7 @@ static int w83977af_probe(int iobase, int irq, int dma)
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int version;
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int i;
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for (i=0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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#ifdef CONFIG_USE_W977_PNP
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/* Enter PnP configuration mode */
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w977_efm_enter(efbase[i]);
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@ -317,7 +316,7 @@ static int w83977af_probe(int iobase, int irq, int dma)
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w977_write_reg(0x70, irq, efbase[i]);
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#ifdef CONFIG_ARCH_NETWINDER
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/* Netwinder uses 1 higher than Linux */
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w977_write_reg(0x74, dma+1, efbase[i]);
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w977_write_reg(0x74, dma + 1, efbase[i]);
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#else
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w977_write_reg(0x74, dma, efbase[i]);
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#endif /* CONFIG_ARCH_NETWINDER */
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@ -333,23 +332,23 @@ static int w83977af_probe(int iobase, int irq, int dma)
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#endif /* CONFIG_USE_W977_PNP */
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/* Disable Advanced mode */
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switch_bank(iobase, SET2);
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outb(iobase+2, 0x00);
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outb(iobase + 2, 0x00);
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/* Turn on UART (global) interrupts */
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switch_bank(iobase, SET0);
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outb(HCR_EN_IRQ, iobase+HCR);
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outb(HCR_EN_IRQ, iobase + HCR);
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/* Switch to advanced mode */
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switch_bank(iobase, SET2);
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outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
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outb(inb(iobase + ADCR1) | ADCR1_ADV_SL, iobase + ADCR1);
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/* Set default IR-mode */
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switch_bank(iobase, SET0);
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outb(HCR_SIR, iobase+HCR);
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outb(HCR_SIR, iobase + HCR);
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/* Read the Advanced IR ID */
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switch_bank(iobase, SET3);
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version = inb(iobase+AUID);
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version = inb(iobase + AUID);
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/* Should be 0x1? */
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if (0x10 == (version & 0xf0)) {
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@ -357,17 +356,17 @@ static int w83977af_probe(int iobase, int irq, int dma)
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/* Set FIFO size to 32 */
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switch_bank(iobase, SET2);
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outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
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outb(ADCR2_RXFS32 | ADCR2_TXFS32, iobase + ADCR2);
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/* Set FIFO threshold to TX17, RX16 */
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switch_bank(iobase, SET0);
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outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
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UFR_EN_FIFO,iobase+UFR);
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outb(UFR_RXTL | UFR_TXTL | UFR_TXF_RST | UFR_RXF_RST |
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UFR_EN_FIFO, iobase + UFR);
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/* Receiver frame length */
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switch_bank(iobase, SET4);
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outb(2048 & 0xff, iobase+6);
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outb((2048 >> 8) & 0x1f, iobase+7);
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outb(2048 & 0xff, iobase + 6);
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outb((2048 >> 8) & 0x1f, iobase + 7);
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/*
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* Init HP HSDL-1100 transceiver.
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@ -382,7 +381,7 @@ static int w83977af_probe(int iobase, int irq, int dma)
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* CIRRX pin 40 connected to pin 37
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*/
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switch_bank(iobase, SET7);
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outb(0x40, iobase+7);
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outb(0x40, iobase + 7);
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net_info_ratelimited("W83977AF (IR) driver loaded. Version: 0x%02x\n",
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version);
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@ -390,7 +389,7 @@ static int w83977af_probe(int iobase, int irq, int dma)
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return 0;
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} else {
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/* Try next extented function register address */
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pr_debug("%s(), Wrong chip version", __func__);
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pr_debug("%s: Wrong chip version\n", __func__);
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}
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}
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return -1;
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@ -408,66 +407,67 @@ static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
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self->io.speed = speed;
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/* Save current bank */
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set = inb(iobase+SSR);
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set = inb(iobase + SSR);
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/* Disable interrupts */
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switch_bank(iobase, SET0);
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outb(0, iobase+ICR);
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outb(0, iobase + ICR);
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/* Select Set 2 */
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switch_bank(iobase, SET2);
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outb(0x00, iobase+ABHL);
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outb(0x00, iobase + ABHL);
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switch (speed) {
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case 9600: outb(0x0c, iobase+ABLL); break;
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case 19200: outb(0x06, iobase+ABLL); break;
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case 38400: outb(0x03, iobase+ABLL); break;
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case 57600: outb(0x02, iobase+ABLL); break;
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case 115200: outb(0x01, iobase+ABLL); break;
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case 9600: outb(0x0c, iobase + ABLL); break;
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case 19200: outb(0x06, iobase + ABLL); break;
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case 38400: outb(0x03, iobase + ABLL); break;
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case 57600: outb(0x02, iobase + ABLL); break;
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case 115200: outb(0x01, iobase + ABLL); break;
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case 576000:
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ir_mode = HCR_MIR_576;
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pr_debug("%s(), handling baud of 576000\n", __func__);
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pr_debug("%s: handling baud of 576000\n", __func__);
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break;
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case 1152000:
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ir_mode = HCR_MIR_1152;
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pr_debug("%s(), handling baud of 1152000\n", __func__);
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pr_debug("%s: handling baud of 1152000\n", __func__);
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break;
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case 4000000:
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ir_mode = HCR_FIR;
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pr_debug("%s(), handling baud of 4000000\n", __func__);
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pr_debug("%s: handling baud of 4000000\n", __func__);
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break;
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default:
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ir_mode = HCR_FIR;
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pr_debug("%s(), unknown baud rate of %d\n", __func__ , speed);
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pr_debug("%s: unknown baud rate of %d\n", __func__, speed);
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break;
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}
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/* Set speed mode */
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switch_bank(iobase, SET0);
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outb(ir_mode, iobase+HCR);
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outb(ir_mode, iobase + HCR);
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/* set FIFO size to 32 */
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switch_bank(iobase, SET2);
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outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
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outb(ADCR2_RXFS32 | ADCR2_TXFS32, iobase + ADCR2);
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/* set FIFO threshold to TX17, RX16 */
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switch_bank(iobase, SET0);
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outb(0x00, iobase+UFR); /* Reset */
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outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
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outb(0xa7, iobase+UFR);
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outb(0x00, iobase + UFR); /* Reset */
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outb(UFR_EN_FIFO, iobase + UFR); /* First we must enable FIFO */
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outb(0xa7, iobase + UFR);
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netif_wake_queue(self->netdev);
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/* Enable some interrupts so we can receive frames */
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switch_bank(iobase, SET0);
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if (speed > PIO_MAX_SPEED) {
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outb(ICR_EFSFI, iobase+ICR);
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outb(ICR_EFSFI, iobase + ICR);
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w83977af_dma_receive(self);
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} else
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outb(ICR_ERBRI, iobase+ICR);
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} else {
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outb(ICR_ERBRI, iobase + ICR);
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}
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|
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/* Restore SSR */
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outb(set, iobase+SSR);
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outb(set, iobase + SSR);
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}
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|
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/*
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@ -477,7 +477,7 @@ static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
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*
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*/
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static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
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struct net_device *dev)
|
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struct net_device *dev)
|
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{
|
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struct w83977af_ir *self;
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__s32 speed;
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@ -489,8 +489,7 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
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|
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iobase = self->io.fir_base;
|
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|
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pr_debug("%s(%ld), skb->len=%d\n", __func__ , jiffies,
|
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(int)skb->len);
|
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pr_debug("%s: %ld, skb->len=%d\n", __func__, jiffies, (int)skb->len);
|
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|
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/* Lock transmit buffer */
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netif_stop_queue(dev);
|
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@ -503,12 +502,12 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
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w83977af_change_speed(self, speed);
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dev_kfree_skb(skb);
|
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return NETDEV_TX_OK;
|
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} else
|
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self->new_speed = speed;
|
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}
|
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self->new_speed = speed;
|
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}
|
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|
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/* Save current set */
|
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set = inb(iobase+SSR);
|
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set = inb(iobase + SSR);
|
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|
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/* Decide if we should use PIO or DMA transfer */
|
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if (self->io.speed > PIO_MAX_SPEED) {
|
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@ -517,15 +516,15 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
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self->tx_buff.len = skb->len;
|
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|
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mtt = irda_get_mtt(skb);
|
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pr_debug("%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
|
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if (mtt > 1000)
|
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mdelay(mtt/1000);
|
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else if (mtt)
|
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pr_debug("%s: %ld, mtt=%d\n", __func__, jiffies, mtt);
|
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if (mtt > 1000)
|
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mdelay(mtt / 1000);
|
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else if (mtt)
|
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udelay(mtt);
|
||||
|
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/* Enable DMA interrupt */
|
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switch_bank(iobase, SET0);
|
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outb(ICR_EDMAI, iobase+ICR);
|
||||
outb(ICR_EDMAI, iobase + ICR);
|
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w83977af_dma_write(self, iobase);
|
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} else {
|
||||
self->tx_buff.data = self->tx_buff.head;
|
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@ -534,12 +533,12 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
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|
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/* Add interrupt on tx low level (will fire immediately) */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(ICR_ETXTHI, iobase+ICR);
|
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outb(ICR_ETXTHI, iobase + ICR);
|
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}
|
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dev_kfree_skb(skb);
|
||||
|
||||
/* Restore set register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
}
|
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@ -553,28 +552,29 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
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static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
|
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{
|
||||
__u8 set;
|
||||
pr_debug("%s(), len=%d\n", __func__ , self->tx_buff.len);
|
||||
|
||||
pr_debug("%s: len=%d\n", __func__, self->tx_buff.len);
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* Disable DMA */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
||||
outb(inb(iobase + HCR) & ~HCR_EN_DMA, iobase + HCR);
|
||||
|
||||
/* Choose transmit DMA channel */
|
||||
switch_bank(iobase, SET2);
|
||||
outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
|
||||
outb(ADCR1_D_CHSW | /*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase + ADCR1);
|
||||
irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
|
||||
DMA_MODE_WRITE);
|
||||
self->io.direction = IO_XMIT;
|
||||
|
||||
/* Enable DMA */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
|
||||
outb(inb(iobase + HCR) | HCR_EN_DMA | HCR_TX_WT, iobase + HCR);
|
||||
|
||||
/* Restore set register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -589,28 +589,27 @@ static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
|
||||
__u8 set;
|
||||
|
||||
/* Save current bank */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
switch_bank(iobase, SET0);
|
||||
if (!(inb_p(iobase+USR) & USR_TSRE)) {
|
||||
pr_debug("%s(), warning, FIFO not empty yet!\n", __func__);
|
||||
if (!(inb_p(iobase + USR) & USR_TSRE)) {
|
||||
pr_debug("%s: warning, FIFO not empty yet!\n", __func__);
|
||||
|
||||
fifo_size -= 17;
|
||||
pr_debug("%s(), %d bytes left in tx fifo\n",
|
||||
__func__ , fifo_size);
|
||||
pr_debug("%s: %d bytes left in tx fifo\n", __func__, fifo_size);
|
||||
}
|
||||
|
||||
/* Fill FIFO with current frame */
|
||||
while ((fifo_size-- > 0) && (actual < len)) {
|
||||
/* Transmit next byte */
|
||||
outb(buf[actual++], iobase+TBR);
|
||||
outb(buf[actual++], iobase + TBR);
|
||||
}
|
||||
|
||||
pr_debug("%s(), fifo_size %d ; %d sent of %d\n",
|
||||
__func__ , fifo_size, actual, len);
|
||||
pr_debug("%s: fifo_size %d ; %d sent of %d\n",
|
||||
__func__, fifo_size, actual, len);
|
||||
|
||||
/* Restore bank */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return actual;
|
||||
}
|
||||
@ -627,31 +626,31 @@ static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
||||
int iobase;
|
||||
__u8 set;
|
||||
|
||||
pr_debug("%s(%ld)\n", __func__ , jiffies);
|
||||
pr_debug("%s: %ld\n", __func__, jiffies);
|
||||
|
||||
IRDA_ASSERT(self != NULL, return;);
|
||||
IRDA_ASSERT(self, return;);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* Disable DMA */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
||||
outb(inb(iobase + HCR) & ~HCR_EN_DMA, iobase + HCR);
|
||||
|
||||
/* Check for underrun! */
|
||||
if (inb(iobase+AUDR) & AUDR_UNDR) {
|
||||
pr_debug("%s(), Transmit underrun!\n", __func__);
|
||||
if (inb(iobase + AUDR) & AUDR_UNDR) {
|
||||
pr_debug("%s: Transmit underrun!\n", __func__);
|
||||
|
||||
self->netdev->stats.tx_errors++;
|
||||
self->netdev->stats.tx_fifo_errors++;
|
||||
|
||||
/* Clear bit, by writing 1 to it */
|
||||
outb(AUDR_UNDR, iobase+AUDR);
|
||||
} else
|
||||
outb(AUDR_UNDR, iobase + AUDR);
|
||||
} else {
|
||||
self->netdev->stats.tx_packets++;
|
||||
|
||||
}
|
||||
|
||||
if (self->new_speed) {
|
||||
w83977af_change_speed(self, self->new_speed);
|
||||
@ -663,7 +662,7 @@ static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
||||
netif_wake_queue(self->netdev);
|
||||
|
||||
/* Restore set */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -681,23 +680,23 @@ static int w83977af_dma_receive(struct w83977af_ir *self)
|
||||
unsigned long flags;
|
||||
__u8 hcr;
|
||||
#endif
|
||||
IRDA_ASSERT(self != NULL, return -1;);
|
||||
IRDA_ASSERT(self, return -1;);
|
||||
|
||||
pr_debug("%s\n", __func__);
|
||||
|
||||
iobase= self->io.fir_base;
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* Disable DMA */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
||||
outb(inb(iobase + HCR) & ~HCR_EN_DMA, iobase + HCR);
|
||||
|
||||
/* Choose DMA Rx, DMA Fairness, and Advanced mode */
|
||||
switch_bank(iobase, SET2);
|
||||
outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
|
||||
iobase+ADCR1);
|
||||
outb((inb(iobase + ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/ | ADCR1_ADV_SL,
|
||||
iobase + ADCR1);
|
||||
|
||||
self->io.direction = IO_RECV;
|
||||
self->rx_buff.data = self->rx_buff.head;
|
||||
@ -720,21 +719,21 @@ static int w83977af_dma_receive(struct w83977af_ir *self)
|
||||
* be finished transmitting yet
|
||||
*/
|
||||
switch_bank(iobase, SET0);
|
||||
outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
|
||||
outb(UFR_RXTL | UFR_TXTL | UFR_RXF_RST | UFR_EN_FIFO, iobase + UFR);
|
||||
self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
|
||||
|
||||
/* Enable DMA */
|
||||
switch_bank(iobase, SET0);
|
||||
#ifdef CONFIG_ARCH_NETWINDER
|
||||
hcr = inb(iobase+HCR);
|
||||
outb(hcr | HCR_EN_DMA, iobase+HCR);
|
||||
hcr = inb(iobase + HCR);
|
||||
outb(hcr | HCR_EN_DMA, iobase + HCR);
|
||||
enable_dma(self->io.dma);
|
||||
spin_unlock_irqrestore(&self->lock, flags);
|
||||
#else
|
||||
outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
|
||||
outb(inb(iobase + HCR) | HCR_EN_DMA, iobase + HCR);
|
||||
#endif
|
||||
/* Restore set */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -761,17 +760,17 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Read status FIFO */
|
||||
switch_bank(iobase, SET5);
|
||||
while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
|
||||
while ((status = inb(iobase + FS_FO)) & FS_FO_FSFDR) {
|
||||
st_fifo->entries[st_fifo->tail].status = status;
|
||||
|
||||
st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL);
|
||||
st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
|
||||
st_fifo->entries[st_fifo->tail].len = inb(iobase + RFLFL);
|
||||
st_fifo->entries[st_fifo->tail].len |= inb(iobase + RFLFH) << 8;
|
||||
|
||||
st_fifo->tail++;
|
||||
st_fifo->len++;
|
||||
@ -814,16 +813,15 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
||||
} else {
|
||||
/* Check if we have transferred all data to memory */
|
||||
switch_bank(iobase, SET0);
|
||||
if (inb(iobase+USR) & USR_RDR) {
|
||||
if (inb(iobase + USR) & USR_RDR)
|
||||
udelay(80); /* Should be enough!? */
|
||||
}
|
||||
|
||||
skb = dev_alloc_skb(len+1);
|
||||
if (skb == NULL) {
|
||||
printk(KERN_INFO
|
||||
"%s(), memory squeeze, dropping frame.\n", __func__);
|
||||
skb = dev_alloc_skb(len + 1);
|
||||
if (!skb) {
|
||||
pr_info("%s: memory squeeze, dropping frame\n",
|
||||
__func__);
|
||||
/* Restore set register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
@ -833,12 +831,12 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
||||
|
||||
/* Copy frame without CRC */
|
||||
if (self->io.speed < 4000000) {
|
||||
skb_put(skb, len-2);
|
||||
skb_put(skb, len - 2);
|
||||
skb_copy_to_linear_data(skb,
|
||||
self->rx_buff.data,
|
||||
len - 2);
|
||||
} else {
|
||||
skb_put(skb, len-4);
|
||||
skb_put(skb, len - 4);
|
||||
skb_copy_to_linear_data(skb,
|
||||
self->rx_buff.data,
|
||||
len - 4);
|
||||
@ -855,7 +853,7 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
||||
}
|
||||
}
|
||||
/* Restore set register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
@ -871,16 +869,16 @@ static void w83977af_pio_receive(struct w83977af_ir *self)
|
||||
__u8 byte = 0x00;
|
||||
int iobase;
|
||||
|
||||
IRDA_ASSERT(self != NULL, return;);
|
||||
IRDA_ASSERT(self, return;);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Receive all characters in Rx FIFO */
|
||||
do {
|
||||
byte = inb(iobase+RBR);
|
||||
byte = inb(iobase + RBR);
|
||||
async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
|
||||
byte);
|
||||
} while (inb(iobase+USR) & USR_RDR); /* Data available */
|
||||
} while (inb(iobase + USR) & USR_RDR); /* Data available */
|
||||
}
|
||||
|
||||
/*
|
||||
@ -896,7 +894,7 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
||||
__u8 set;
|
||||
int iobase;
|
||||
|
||||
pr_debug("%s(), isr=%#x\n", __func__ , isr);
|
||||
pr_debug("%s: isr=%#x\n", __func__, isr);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
/* Transmit FIFO low on data */
|
||||
@ -916,10 +914,10 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
||||
if (self->tx_buff.len > 0) {
|
||||
new_icr |= ICR_ETXTHI;
|
||||
} else {
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
switch_bank(iobase, SET0);
|
||||
outb(AUDR_SFEND, iobase+AUDR);
|
||||
outb(set, iobase+SSR);
|
||||
outb(AUDR_SFEND, iobase + AUDR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
self->netdev->stats.tx_packets++;
|
||||
|
||||
@ -932,7 +930,7 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
||||
if (isr & ISR_TXEMP_I) {
|
||||
/* Check if we need to change the speed? */
|
||||
if (self->new_speed) {
|
||||
pr_debug("%s(), Changing speed!\n", __func__);
|
||||
pr_debug("%s: Changing speed!\n", __func__);
|
||||
w83977af_change_speed(self, self->new_speed);
|
||||
self->new_speed = 0;
|
||||
}
|
||||
@ -965,12 +963,11 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
||||
int iobase;
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* End of frame detected in FIFO */
|
||||
if (isr & (ISR_FEND_I|ISR_FSF_I)) {
|
||||
if (isr & (ISR_FEND_I | ISR_FSF_I)) {
|
||||
if (w83977af_dma_receive_complete(self)) {
|
||||
|
||||
/* Wait for next status FIFO interrupt */
|
||||
new_icr |= ICR_EFSFI;
|
||||
} else {
|
||||
@ -978,11 +975,11 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
||||
|
||||
/* Set timer value, resolution 1 ms */
|
||||
switch_bank(iobase, SET4);
|
||||
outb(0x01, iobase+TMRL); /* 1 ms */
|
||||
outb(0x00, iobase+TMRH);
|
||||
outb(0x01, iobase + TMRL); /* 1 ms */
|
||||
outb(0x00, iobase + TMRH);
|
||||
|
||||
/* Start timer */
|
||||
outb(IR_MSL_EN_TMR, iobase+IR_MSL);
|
||||
outb(IR_MSL_EN_TMR, iobase + IR_MSL);
|
||||
|
||||
new_icr |= ICR_ETMRI;
|
||||
}
|
||||
@ -991,7 +988,7 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
||||
if (isr & ISR_TMR_I) {
|
||||
/* Disable timer */
|
||||
switch_bank(iobase, SET4);
|
||||
outb(0, iobase+IR_MSL);
|
||||
outb(0, iobase + IR_MSL);
|
||||
|
||||
/* Clear timer event */
|
||||
/* switch_bank(iobase, SET0); */
|
||||
@ -1026,7 +1023,7 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
||||
}
|
||||
|
||||
/* Restore set */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return new_icr;
|
||||
}
|
||||
@ -1049,24 +1046,24 @@ static irqreturn_t w83977af_interrupt(int irq, void *dev_id)
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Save current bank */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
switch_bank(iobase, SET0);
|
||||
|
||||
icr = inb(iobase+ICR);
|
||||
isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
|
||||
icr = inb(iobase + ICR);
|
||||
isr = inb(iobase + ISR) & icr; /* Mask out the interesting ones */
|
||||
|
||||
outb(0, iobase+ICR); /* Disable interrupts */
|
||||
outb(0, iobase + ICR); /* Disable interrupts */
|
||||
|
||||
if (isr) {
|
||||
/* Dispatch interrupt handler for the current speed */
|
||||
if (self->io.speed > PIO_MAX_SPEED )
|
||||
if (self->io.speed > PIO_MAX_SPEED)
|
||||
icr = w83977af_fir_interrupt(self, isr);
|
||||
else
|
||||
icr = w83977af_sir_interrupt(self, isr);
|
||||
}
|
||||
|
||||
outb(icr, iobase+ICR); /* Restore (new) interrupts */
|
||||
outb(set, iobase+SSR); /* Restore bank register */
|
||||
outb(icr, iobase + ICR); /* Restore (new) interrupts */
|
||||
outb(set, iobase + SSR); /* Restore bank register */
|
||||
return IRQ_RETVAL(isr);
|
||||
}
|
||||
|
||||
@ -1082,21 +1079,22 @@ static int w83977af_is_receiving(struct w83977af_ir *self)
|
||||
int iobase;
|
||||
__u8 set;
|
||||
|
||||
IRDA_ASSERT(self != NULL, return FALSE;);
|
||||
IRDA_ASSERT(self, return FALSE;);
|
||||
|
||||
if (self->io.speed > 115200) {
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
/* Check if rx FIFO is not empty */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
switch_bank(iobase, SET2);
|
||||
if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
|
||||
if ((inb(iobase + RXFDTH) & 0x3f) != 0) {
|
||||
/* We are receiving something */
|
||||
status = TRUE;
|
||||
}
|
||||
outb(set, iobase+SSR);
|
||||
} else
|
||||
outb(set, iobase + SSR);
|
||||
} else {
|
||||
status = (self->rx_buff.state != OUTSIDE_FRAME);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
@ -1114,16 +1112,15 @@ static int w83977af_net_open(struct net_device *dev)
|
||||
char hwname[32];
|
||||
__u8 set;
|
||||
|
||||
|
||||
IRDA_ASSERT(dev != NULL, return -1;);
|
||||
IRDA_ASSERT(dev, return -1;);
|
||||
self = netdev_priv(dev);
|
||||
|
||||
IRDA_ASSERT(self != NULL, return 0;);
|
||||
IRDA_ASSERT(self, return 0;);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
|
||||
(void *) dev)) {
|
||||
(void *)dev)) {
|
||||
return -EAGAIN;
|
||||
}
|
||||
/*
|
||||
@ -1136,18 +1133,19 @@ static int w83977af_net_open(struct net_device *dev)
|
||||
}
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* Enable some interrupts so we can receive frames again */
|
||||
switch_bank(iobase, SET0);
|
||||
if (self->io.speed > 115200) {
|
||||
outb(ICR_EFSFI, iobase+ICR);
|
||||
outb(ICR_EFSFI, iobase + ICR);
|
||||
w83977af_dma_receive(self);
|
||||
} else
|
||||
outb(ICR_ERBRI, iobase+ICR);
|
||||
} else {
|
||||
outb(ICR_ERBRI, iobase + ICR);
|
||||
}
|
||||
|
||||
/* Restore bank register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
/* Ready to play! */
|
||||
netif_start_queue(dev);
|
||||
@ -1176,11 +1174,11 @@ static int w83977af_net_close(struct net_device *dev)
|
||||
int iobase;
|
||||
__u8 set;
|
||||
|
||||
IRDA_ASSERT(dev != NULL, return -1;);
|
||||
IRDA_ASSERT(dev, return -1;);
|
||||
|
||||
self = netdev_priv(dev);
|
||||
|
||||
IRDA_ASSERT(self != NULL, return 0;);
|
||||
IRDA_ASSERT(self, return 0;);
|
||||
|
||||
iobase = self->io.fir_base;
|
||||
|
||||
@ -1195,17 +1193,17 @@ static int w83977af_net_close(struct net_device *dev)
|
||||
disable_dma(self->io.dma);
|
||||
|
||||
/* Save current set */
|
||||
set = inb(iobase+SSR);
|
||||
set = inb(iobase + SSR);
|
||||
|
||||
/* Disable interrupts */
|
||||
switch_bank(iobase, SET0);
|
||||
outb(0, iobase+ICR);
|
||||
outb(0, iobase + ICR);
|
||||
|
||||
free_irq(self->io.irq, dev);
|
||||
free_dma(self->io.dma);
|
||||
|
||||
/* Restore bank register */
|
||||
outb(set, iobase+SSR);
|
||||
outb(set, iobase + SSR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1218,18 +1216,18 @@ static int w83977af_net_close(struct net_device *dev)
|
||||
*/
|
||||
static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
||||
{
|
||||
struct if_irda_req *irq = (struct if_irda_req *) rq;
|
||||
struct if_irda_req *irq = (struct if_irda_req *)rq;
|
||||
struct w83977af_ir *self;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
|
||||
IRDA_ASSERT(dev != NULL, return -1;);
|
||||
IRDA_ASSERT(dev, return -1;);
|
||||
|
||||
self = netdev_priv(dev);
|
||||
|
||||
IRDA_ASSERT(self != NULL, return -1;);
|
||||
IRDA_ASSERT(self, return -1;);
|
||||
|
||||
pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
|
||||
pr_debug("%s: %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
|
||||
|
||||
spin_lock_irqsave(&self->lock, flags);
|
||||
|
||||
@ -1263,7 +1261,6 @@ MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
|
||||
MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
|
||||
module_param(qos_mtt_bits, int, 0);
|
||||
MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time");
|
||||
module_param_array(io, int, NULL, 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user