mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 23:14:31 +08:00
OMAPDSS: fix rounding when calculating fclk rate
"clk: divider: fix rate calculation for fractional rates" patch (and similar for TI specific divider) fixes the clk-divider's rounding. This patch updates the DSS driver to round the rates accordingly. This fixes the DSS's warnings about clock rate mismatch, and also fixes the wrong fclk rate being set. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com>
This commit is contained in:
parent
8d018647e0
commit
d0e224f996
@ -457,7 +457,7 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min,
|
||||
fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
|
||||
|
||||
for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
|
||||
fck = prate / fckd * m;
|
||||
fck = DIV_ROUND_UP(prate, fckd) * m;
|
||||
|
||||
if (func(fck, data))
|
||||
return true;
|
||||
@ -506,7 +506,7 @@ static int dss_setup_default_clock(void)
|
||||
|
||||
fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
|
||||
max_dss_fck);
|
||||
fck = prate / fck_div * dss.feat->dss_fck_multiplier;
|
||||
fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
|
||||
}
|
||||
|
||||
r = dss_set_fck_rate(fck);
|
||||
|
Loading…
Reference in New Issue
Block a user