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perf: imx_perf: add support for i.MX95 platform

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i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
read beat and write beat filter capabilities. This will add support for
i.MX95 and enhance the driver to support specific filter handling for it.

Usage:

For read beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=0x00f,axi_id=0x00c/

For write beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=0x00f,axi_id=0x00c/

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://lore.kernel.org/r/20240529080358.703784-6-xu.yang_2@nxp.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Xu Yang 2024-05-29 16:03:56 +08:00 committed by Will Deacon
parent ac9aa295f7
commit d0d7c66c53
1 changed files with 86 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
drivers/perf/fsl_imx9_ddr_perf.c
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@ -17,9 +17,19 @@
#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
#define PMCFG2 0x04
#define MX93_PMCFG2_ID GENMASK(17, 0)
#define PMCFG3 0x08
#define PMCFG4 0x0C
#define PMCFG5 0x10
#define PMCFG6 0x14
#define MX95_PMCFG_ID_MASK GENMASK(9, 0)
#define MX95_PMCFG_ID GENMASK(25, 16)
/* Global control register affects all counters and takes priority over local control registers */
#define PMGC0 0x40
/* Global control register bits */
@ -75,13 +85,23 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = {
.identifier = "imx93",
};
static const struct imx_ddr_devtype_data imx95_devtype_data = {
.identifier = "imx95",
};
static inline bool is_imx93(struct ddr_pmu *pmu)
{
return pmu->devtype_data == &imx93_devtype_data;
}
static inline bool is_imx95(struct ddr_pmu *pmu)
{
return pmu->devtype_data == &imx95_devtype_data;
}
static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
{.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
{ .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
{ .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
@ -158,6 +178,9 @@ static ssize_t ddr_pmu_event_show(struct device *dev,
#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \
DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data)
static struct attribute *ddr_perf_events_attrs[] = {
/* counter0 cycles event */
IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
@ -204,6 +227,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/
/* counter3 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
@ -216,6 +240,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/
/* counter4 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
@ -228,6 +253,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/
/* counter5 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
@ -239,6 +265,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)),
IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/
/* counter6 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)),
@ -432,6 +459,57 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
writel_relaxed(pmcfg2, pmu->base + PMCFG2);
}
static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
int counter, int axi_id, int axi_mask)
{
u32 pmcfg1, pmcfg, offset = 0;
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
if (event == 73) {
switch (counter) {
case 2:
pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
offset = PMCFG3;
break;
case 3:
pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
offset = PMCFG4;
break;
case 4:
pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
offset = PMCFG5;
break;
case 5:
pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
offset = PMCFG6;
break;
}
} else {
switch (counter) {
case 2:
pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
break;
case 3:
case 4:
case 5:
pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
break;
}
}
writel_relaxed(pmcfg1, pmu->base + PMCFG1);
if (offset) {
pmcfg = readl_relaxed(pmu->base + offset);
pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) |
FIELD_PREP(MX95_PMCFG_ID, axi_id));
writel_relaxed(pmcfg, pmu->base + offset);
}
}
static void ddr_perf_event_update(struct perf_event *event)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@ -541,8 +619,13 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
/* read trans, write trans, read beat */
imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
if (is_imx93(pmu))
/* read trans, write trans, read beat */
imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
if (is_imx95(pmu))
/* write beat, read beat2, read beat1, read beat */
imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
if (flags & PERF_EF_START)
ddr_perf_event_start(event, flags);