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AT91 fixes #1 for 5.15:
- Fixes for newly introduced SAMA7G5 and its Power Management code. Associated core peripherals need to be instantiated in DT for benefiting from best PM support like Backup mode with DDR in Self-Refresh. - Add chip ID for SAMA7G5 for easing the kernel log identification. - Avoid Camera Sensor probe error on sama5d27 som1 ek board. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYUDJYQAKCRAfOrpwrNPN DAAEAQCFIBeK4ll4yXwioU+4hX7RjP/wx5rKJjwGQOx7cHctyAEAz2951P5K6erg 6+qE4ZnsUjlo+6XeOTIuQouz57aKGwk= =vVRX -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmFAz0EACgkQmmx57+YA GNkapw/+KziVcbfva3GAWfYA10MuJPLg8EAtC8x9Q6knOWmxmg7apZS/zm4F9+ej T5EVsW6OcTQUexV6LMiB9JAB2jaawtF2wGzP2KIZdtz9YCYrTxsCTmXQoc/Yccmi CoBMYzkDq04i+y+SBBFFifUOUPWlEnH92wwGAnN+NvUeT2W7RAinwqf8ZtVrRTOk VFmjiKYhsHy2rj9huhNIm2v4na/ay/3Lun7gS1cKnNvfV5X4ua0duswnf4w5j1TD QHtkWTQ5/q4AZpXAbUwURNZ7p7Qq6yQE4OVAP3lCVMPmwArUHKRrah42IDwik1Ou 7KrVLMyq2BsGGu1vwHT2s1RGGpIHqs2IXv/WMRSBs6VweU9DEOmuRFg+pEYyzBcL Q/wxarJY7uyJVcUbLj5j5t8qJXdJAcc3vwdVh8uD5jQIT9Ks+CESfMnu/C+KuYx/ cuTffJyfrzRKJN7gg6BxMby865XsEgKTWYqg/NS4X+YSzBRiP6UytsjK1xQ5L8Ac UnW66w7BpmLfvFngOhzF9zD3P0Yad9lyCYySlemKTDHkcFYPBWwGYSfTocc/z4Zg WgOlQbUvX+C8LHH0yactzaTb1BUb03DXVja4GUwwYd3AYOi8sc9JXEunnoKBkVBh xr4VaIoo6PKQtUQNTgUyjciBCi3scWP4axHtAcq73P2gbEnyL6c= =C+No -----END PGP SIGNATURE----- Merge tag 'at91-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes AT91 fixes #1 for 5.15: - Fixes for newly introduced SAMA7G5 and its Power Management code. Associated core peripherals need to be instantiated in DT for benefiting from best PM support like Backup mode with DDR in Self-Refresh. - Add chip ID for SAMA7G5 for easing the kernel log identification. - Avoid Camera Sensor probe error on sama5d27 som1 ek board. * tag 'at91-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama5d2_som1_ek: disable ISC node by default ARM: at91: pm: switch backup area to vbat in backup mode ARM: dts: at91: sama7g5: add chipid ARM: dts: at91: sama7g5: add shdwc node ARM: dts: at91: sama7g5: add securam node ARM: dts: at91: sama7g5: add ram controllers ARM: at91: pm: do not panic if ram controllers are not enabled Link: https://lore.kernel.org/r/20210914162314.54347-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d0c624c030
@ -71,7 +71,6 @@
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isc: isc@f0008000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
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status = "okay";
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};
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qspi1: spi@f0024000 {
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@ -634,6 +634,15 @@
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pinctrl-0 = <&pinctrl_sdmmc2_default>;
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};
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&shdwc {
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atmel,shdwc-debouncer = <976>;
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status = "okay";
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input@0 {
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reg = <0>;
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};
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};
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&spdifrx {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spdifrx_default>;
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@ -75,6 +75,17 @@
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#size-cells = <1>;
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ranges;
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securam: securam@e0000000 {
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compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
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reg = <0xe0000000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x4000>;
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no-memory-wc;
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status = "okay";
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};
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secumod: secumod@e0004000 {
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compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
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reg = <0xe0004000 0x4000>;
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@ -111,6 +122,17 @@
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clock-names = "td_slck", "md_slck", "main_xtal";
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};
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shdwc: shdwc@e001d010 {
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compatible = "microchip,sama7g5-shdwc", "syscon";
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reg = <0xe001d010 0x10>;
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clocks = <&clk32k 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtt-timer;
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status = "disabled";
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};
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rtt: rtt@e001d020 {
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compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
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reg = <0xe001d020 0x30>;
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@ -137,6 +159,11 @@
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clocks = <&clk32k 0>;
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};
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chipid@e0020000 {
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compatible = "microchip,sama7g5-chipid";
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reg = <0xe0020000 0x8>;
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};
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sdmmc0: mmc@e1204000 {
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compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe1204000 0x4000>;
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@ -515,6 +542,18 @@
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};
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};
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uddrc: uddrc@e3800000 {
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compatible = "microchip,sama7g5-uddrc";
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reg = <0xe3800000 0x4000>;
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status = "okay";
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};
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ddr3phy: ddr3phy@e3804000 {
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compatible = "microchip,sama7g5-ddr3phy";
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reg = <0xe3804000 0x1000>;
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status = "okay";
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};
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gic: interrupt-controller@e8c11000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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@ -47,12 +47,26 @@ struct at91_pm_bu {
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unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
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};
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/*
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* struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
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* @pswbu: power switch BU control registers
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*/
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struct at91_pm_sfrbu_regs {
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struct {
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u32 key;
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u32 ctrl;
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u32 state;
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u32 softsw;
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} pswbu;
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};
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/**
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* struct at91_soc_pm - AT91 SoC power management data structure
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* @config_shdwc_ws: wakeup sources configuration function for SHDWC
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* @config_pmc_ws: wakeup srouces configuration function for PMC
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* @ws_ids: wakup sources of_device_id array
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* @data: PM data to be used on last phase of suspend
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* @sfrbu_regs: SFRBU registers mapping
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* @bu: backup unit mapped data (for backup mode)
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* @memcs: memory chip select
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*/
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@ -62,6 +76,7 @@ struct at91_soc_pm {
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const struct of_device_id *ws_ids;
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struct at91_pm_bu *bu;
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struct at91_pm_data data;
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struct at91_pm_sfrbu_regs sfrbu_regs;
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void *memcs;
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};
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@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned long val)
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return 0;
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}
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static void at91_pm_switch_ba_to_vbat(void)
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{
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unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
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unsigned int val;
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/* Just for safety. */
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if (!soc_pm.data.sfrbu)
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return;
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val = readl(soc_pm.data.sfrbu + offset);
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/* Already on VBAT. */
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if (!(val & soc_pm.sfrbu_regs.pswbu.state))
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return;
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val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
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val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
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writel(val, soc_pm.data.sfrbu + offset);
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/* Wait for update. */
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val = readl(soc_pm.data.sfrbu + offset);
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while (val & soc_pm.sfrbu_regs.pswbu.state)
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val = readl(soc_pm.data.sfrbu + offset);
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}
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static void at91_pm_suspend(suspend_state_t state)
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{
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if (soc_pm.data.mode == AT91_PM_BACKUP) {
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at91_pm_switch_ba_to_vbat();
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cpu_suspend(0, at91_suspend_finish);
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/* The SRAM is lost between suspend cycles */
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@ -589,18 +631,22 @@ static const struct of_device_id ramc_phy_ids[] __initconst = {
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{ /* Sentinel. */ },
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};
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static __init void at91_dt_ramc(bool phy_mandatory)
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static __init int at91_dt_ramc(bool phy_mandatory)
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{
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struct device_node *np;
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const struct of_device_id *of_id;
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int idx = 0;
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void *standby = NULL;
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const struct ramc_info *ramc;
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int ret;
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for_each_matching_node_and_match(np, ramc_ids, &of_id) {
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soc_pm.data.ramc[idx] = of_iomap(np, 0);
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if (!soc_pm.data.ramc[idx])
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panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
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if (!soc_pm.data.ramc[idx]) {
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pr_err("unable to map ramc[%d] cpu registers\n", idx);
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ret = -ENOMEM;
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goto unmap_ramc;
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}
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ramc = of_id->data;
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if (ramc) {
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@ -612,25 +658,42 @@ static __init void at91_dt_ramc(bool phy_mandatory)
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idx++;
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}
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if (!idx)
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panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
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if (!idx) {
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pr_err("unable to find compatible ram controller node in dtb\n");
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ret = -ENODEV;
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goto unmap_ramc;
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}
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/* Lookup for DDR PHY node, if any. */
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for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
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soc_pm.data.ramc_phy = of_iomap(np, 0);
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if (!soc_pm.data.ramc_phy)
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panic(pr_fmt("unable to map ramc phy cpu registers\n"));
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if (!soc_pm.data.ramc_phy) {
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pr_err("unable to map ramc phy cpu registers\n");
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ret = -ENOMEM;
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goto unmap_ramc;
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}
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}
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if (phy_mandatory && !soc_pm.data.ramc_phy)
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panic(pr_fmt("DDR PHY is mandatory!\n"));
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if (phy_mandatory && !soc_pm.data.ramc_phy) {
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pr_err("DDR PHY is mandatory!\n");
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ret = -ENODEV;
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goto unmap_ramc;
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}
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if (!standby) {
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pr_warn("ramc no standby function available\n");
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return;
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return 0;
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}
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at91_cpuidle_device.dev.platform_data = standby;
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return 0;
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unmap_ramc:
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while (idx)
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iounmap(soc_pm.data.ramc[--idx]);
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return ret;
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}
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static void at91rm9200_idle(void)
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@ -1017,6 +1080,8 @@ static void __init at91_pm_init(void (*pm_idle)(void))
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void __init at91rm9200_pm_init(void)
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{
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
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return;
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@ -1028,7 +1093,9 @@ void __init at91rm9200_pm_init(void)
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soc_pm.data.standby_mode = AT91_PM_STANDBY;
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soc_pm.data.suspend_mode = AT91_PM_ULP0;
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at91_dt_ramc(false);
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ret = at91_dt_ramc(false);
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if (ret)
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return;
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/*
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* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
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@ -1046,13 +1113,17 @@ void __init sam9x60_pm_init(void)
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static const int iomaps[] __initconst = {
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[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
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};
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
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return;
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at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
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at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
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at91_dt_ramc(false);
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ret = at91_dt_ramc(false);
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if (ret)
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return;
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at91_pm_init(NULL);
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soc_pm.ws_ids = sam9x60_ws_ids;
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@ -1061,6 +1132,8 @@ void __init sam9x60_pm_init(void)
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void __init at91sam9_pm_init(void)
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{
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
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return;
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@ -1072,7 +1145,10 @@ void __init at91sam9_pm_init(void)
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soc_pm.data.standby_mode = AT91_PM_STANDBY;
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soc_pm.data.suspend_mode = AT91_PM_ULP0;
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at91_dt_ramc(false);
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ret = at91_dt_ramc(false);
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if (ret)
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return;
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at91_pm_init(at91sam9_idle);
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}
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@ -1081,12 +1157,16 @@ void __init sama5_pm_init(void)
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static const int modes[] __initconst = {
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AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
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};
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_SAMA5))
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return;
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at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
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at91_dt_ramc(false);
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ret = at91_dt_ramc(false);
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if (ret)
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return;
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at91_pm_init(NULL);
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}
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@ -1101,18 +1181,27 @@ void __init sama5d2_pm_init(void)
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[AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
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AT91_PM_IOMAP(SFRBU),
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};
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
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return;
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at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
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at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
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at91_dt_ramc(false);
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ret = at91_dt_ramc(false);
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if (ret)
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return;
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at91_pm_init(NULL);
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soc_pm.ws_ids = sama5d2_ws_ids;
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soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
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soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
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soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
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soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
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soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
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soc_pm.sfrbu_regs.pswbu.state = BIT(3);
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}
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void __init sama7_pm_init(void)
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@ -1127,18 +1216,27 @@ void __init sama7_pm_init(void)
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[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
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AT91_PM_IOMAP(SHDWC),
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};
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int ret;
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if (!IS_ENABLED(CONFIG_SOC_SAMA7))
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return;
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at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
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at91_dt_ramc(true);
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ret = at91_dt_ramc(true);
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if (ret)
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return;
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at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
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at91_pm_init(NULL);
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soc_pm.ws_ids = sama7g5_ws_ids;
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soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
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soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
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soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
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soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
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soc_pm.sfrbu_regs.pswbu.state = BIT(2);
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}
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static int __init at91_pm_modes_select(char *str)
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Block a user