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dma: mxs-dma: enable channel in device_issue_pending call
Enable channel in device_issue_pending call, so that the order between cookie assignment and channel enabling can be ensured naturally. It fixes the mxs gpmi-nand breakage which is caused by the incorrect order of cookie assigning and channel enabling. Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Huang Shijie <b32955@freescale.com> Tested-by <samgandhi9@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
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@ -201,10 +201,6 @@ static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
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static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
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mxs_dma_enable_chan(mxs_chan);
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return dma_cookie_assign(tx);
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}
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@ -558,9 +554,9 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
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static void mxs_dma_issue_pending(struct dma_chan *chan)
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{
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/*
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* Nothing to do. We only have a single descriptor.
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*/
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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mxs_dma_enable_chan(mxs_chan);
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}
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static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
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@ -363,6 +363,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(host->dmach);
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return;
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out:
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@ -403,6 +404,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(host->dmach);
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return;
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out:
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@ -531,6 +533,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
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goto out;
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dmaengine_submit(desc);
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dma_async_issue_pending(host->dmach);
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return;
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out:
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dev_warn(mmc_dev(host->mmc),
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@ -266,6 +266,7 @@ int start_dma_without_bch_irq(struct gpmi_nand_data *this,
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desc->callback = dma_irq_callback;
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desc->callback_param = this;
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dmaengine_submit(desc);
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dma_async_issue_pending(get_dma_chan(this));
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/* Wait for the interrupt from the DMA block. */
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err = wait_for_completion_timeout(dma_c, msecs_to_jiffies(1000));
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