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perf vendor events arm64: Reference common and uarch events for Ampere eMag

Browse Source 
Reduce duplication in the JSONs by referencing standard events from
armv8-common-and-microarch.json

In general the "PublicDescription" fields are not modified when somewhat
significantly worded differently than the standard.

Apart from that, description and names for events slightly different to
standard are changed (to standard) for consistency.

Note that names for events 0x34 and 0x35 are non-standard and remain
unchanged. Those events came from the following originally:

  4c2479c67b/Documentation/arm64/eMAG-ARM-CoreImpDefined.pdf

Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Will Deacon <will@kernel.org>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Nakamura, Shunsuke/中村 俊介 <nakamura.shun@fujitsu.com>
Cc: mathieu.poirier@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@openeuler.org
Link: https://lore.kernel.org/r/1611835236-34696-4-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
John Garry 2021-01-28 20:00:35 +08:00 committed by Arnaldo Carvalho de Melo
parent c77669662f
commit d02d5dc882
7 changed files with 31 additions and 97 deletions
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8
tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
View File

@ -9,15 +9,11 @@
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"PublicDescription": "Mispredicted or not predicted branch speculatively executed",
"EventCode": "0x10",
"EventName": "BR_MIS_PRED",
"ArchStdEvent": "BR_MIS_PRED",
"BriefDescription": "Branch mispredicted"
},
{
"PublicDescription": "Predictable branch speculatively executed",
"EventCode": "0x12",
"EventName": "BR_PRED",
"ArchStdEvent": "BR_PRED",
"BriefDescription": "Predictable branch"
}
]

5
tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
View File

@ -18,9 +18,6 @@
"ArchStdEvent": "BUS_ACCESS_PERIPH"
},
{
"PublicDescription": "Bus access",
"EventCode": "0x19",
"EventName": "BUS_ACCESS",
"BriefDescription": "Bus access"
"ArchStdEvent": "BUS_ACCESS",
}
]

56
tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
View File

@ -39,70 +39,40 @@
"ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"PublicDescription": "Level 1 instruction cache refill",
"EventCode": "0x01",
"EventName": "L1I_CACHE_REFILL",
"BriefDescription": "L1I cache refill"
"ArchStdEvent": "L1I_CACHE_REFILL",
},
{
"PublicDescription": "Level 1 instruction TLB refill",
"EventCode": "0x02",
"EventName": "L1I_TLB_REFILL",
"BriefDescription": "L1I TLB refill"
"ArchStdEvent": "L1I_TLB_REFILL",
},
{
"PublicDescription": "Level 1 data cache refill",
"EventCode": "0x03",
"EventName": "L1D_CACHE_REFILL",
"BriefDescription": "L1D cache refill"
"ArchStdEvent": "L1D_CACHE_REFILL",
},
{
"PublicDescription": "Level 1 data cache access",
"EventCode": "0x04",
"EventName": "L1D_CACHE_ACCESS",
"BriefDescription": "L1D cache access"
"ArchStdEvent": "L1D_CACHE",
},
{
"PublicDescription": "Level 1 data TLB refill",
"EventCode": "0x05",
"EventName": "L1D_TLB_REFILL",
"BriefDescription": "L1D TLB refill"
"ArchStdEvent": "L1D_TLB_REFILL",
},
{
"PublicDescription": "Level 1 instruction cache access",
"EventCode": "0x14",
"EventName": "L1I_CACHE_ACCESS",
"BriefDescription": "L1I cache access"
"ArchStdEvent": "L1I_CACHE",
},
{
"PublicDescription": "Level 2 data cache access",
"EventCode": "0x16",
"EventName": "L2D_CACHE_ACCESS",
"BriefDescription": "L2D cache access"
"ArchStdEvent": "L2D_CACHE",
},
{
"PublicDescription": "Level 2 data refill",
"EventCode": "0x17",
"EventName": "L2D_CACHE_REFILL",
"BriefDescription": "L2D cache refill"
"ArchStdEvent": "L2D_CACHE_REFILL",
},
{
"PublicDescription": "Level 2 data cache, Write-Back",
"EventCode": "0x18",
"EventName": "L2D_CACHE_WB",
"BriefDescription": "L2D cache Write-Back"
"ArchStdEvent": "L2D_CACHE_WB",
},
{
"PublicDescription": "Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB",
"EventCode": "0x25",
"EventName": "L1D_TLB_ACCESS",
"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
"ArchStdEvent": "L1D_TLB",
"BriefDescription": "L1D TLB access"
},
{
"PublicDescription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB",
"EventCode": "0x26",
"EventName": "L1I_TLB_ACCESS",
"BriefDescription": "L1I TLB access"
"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
"ArchStdEvent": "L1I_TLB",
},
{
"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",

4
tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
View File

@ -1,9 +1,7 @@
[
{
"PublicDescription": "The number of core clock cycles",
"EventCode": "0x11",
"EventName": "CPU_CYCLES",
"BriefDescription": "Clock cycles"
"ArchStdEvent": "CPU_CYCLES",
},
{
"PublicDescription": "FSU clocking gated off cycle",

10
tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
View File

@ -36,15 +36,9 @@
"ArchStdEvent": "EXC_TRAP_FIQ"
},
{
"PublicDescription": "Exception taken",
"EventCode": "0x09",
"EventName": "EXC_TAKEN",
"BriefDescription": "Exception taken"
"ArchStdEvent": "EXC_TAKEN",
},
{
"PublicDescription": "Instruction architecturally executed, condition check pass, exception return",
"EventCode": "0x0a",
"EventName": "EXC_RETURN",
"BriefDescription": "Exception return"
"ArchStdEvent": "EXC_RETURN",
}
]

34
tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
View File

@ -40,45 +40,29 @@
},
{
"PublicDescription": "Instruction architecturally executed, software increment",
"EventCode": "0x00",
"EventName": "SW_INCR",
"ArchStdEvent": "SW_INCR",
"BriefDescription": "Software increment"
},
{
"PublicDescription": "Instruction architecturally executed",
"EventCode": "0x08",
"EventName": "INST_RETIRED",
"BriefDescription": "Instruction retired"
"ArchStdEvent": "INST_RETIRED",
},
{
"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR",
"EventCode": "0x0b",
"EventName": "CID_WRITE_RETIRED",
"ArchStdEvent": "CID_WRITE_RETIRED",
"BriefDescription": "Write to CONTEXTIDR"
},
{
"PublicDescription": "Operation speculatively executed",
"EventCode": "0x1b",
"EventName": "INST_SPEC",
"BriefDescription": "Speculatively executed"
"ArchStdEvent": "INST_SPEC",
},
{
"PublicDescription": "Instruction architecturally executed (condition check pass), write to TTBR",
"EventCode": "0x1c",
"EventName": "TTBR_WRITE_RETIRED",
"BriefDescription": "Instruction executed, TTBR write"
"ArchStdEvent": "TTBR_WRITE_RETIRED",
},
{
"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",
"EventCode": "0x21",
"EventName": "BR_RETIRED",
"BriefDescription": "Branch retired"
"PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",
"ArchStdEvent": "BR_RETIRED",
},
{
"PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",
"EventCode": "0x22",
"EventName": "BR_MISPRED_RETIRED",
"BriefDescription": "Mispredicted branch retired"
"PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",
"ArchStdEvent": "BR_MIS_PRED_RETIRED",
},
{
"PublicDescription": "Operation speculatively executed, NOP",

11
tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
View File

@ -15,15 +15,10 @@
"ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
"PublicDescription": "Data memory access",
"EventCode": "0x13",
"EventName": "MEM_ACCESS",
"BriefDescription": "Memory access"
"ArchStdEvent": "MEM_ACCESS",
},
{
"PublicDescription": "Local memory error. This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
"EventCode": "0x1a",
"EventName": "MEM_ERROR",
"BriefDescription": "Memory error"
"PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
"ArchStdEvent": "MEMORY_ERROR",
}
]