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ath9k_hw: add helpers for processing the AR9003 INI
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Luis R. Rodriguez
John W. Linville
parent
13ce3e997c
commit
cffb5e49a1
@ -186,7 +186,40 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
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static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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u32 phymode;
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u32 enableDacFifo = 0;
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enableDacFifo =
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(REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
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/* Enable 11n HT, 20 MHz */
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phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
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AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
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/* Configure baseband for dynamic 20/40 operation */
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if (IS_CHAN_HT40(chan)) {
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phymode |= AR_PHY_GC_DYN2040_EN;
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/* Configure control (primary) channel at +-10MHz */
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if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
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(chan->chanmode == CHANNEL_G_HT40PLUS))
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phymode |= AR_PHY_GC_DYN2040_PRI_CH;
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}
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/* make sure we preserve INI settings */
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phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
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/* turn off Green Field detection for STA for now */
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phymode &= ~AR_PHY_GC_GF_DETECT_EN;
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REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
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/* Configure MAC for 20/40 operation */
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ath9k_hw_set11nmac2040(ah);
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/* global transmit timeout (25 TUs default)*/
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REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
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/* carrier sense timeout */
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REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
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}
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static void ar9003_hw_init_bb(struct ath_hw *ah,
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@ -195,11 +228,158 @@ static void ar9003_hw_init_bb(struct ath_hw *ah,
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/* TODO */
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}
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void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
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{
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switch (rx) {
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case 0x5:
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REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
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AR_PHY_SWAP_ALT_CHAIN);
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case 0x3:
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case 0x1:
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case 0x2:
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case 0x7:
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REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
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REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
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break;
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default:
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break;
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}
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REG_WRITE(ah, AR_SELFGEN_MASK, tx);
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if (tx == 0x5) {
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REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
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AR_PHY_SWAP_ALT_CHAIN);
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}
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}
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/*
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* Override INI values with chip specific configuration.
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*/
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static void ar9003_hw_override_ini(struct ath_hw *ah)
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{
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u32 val;
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/*
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* Set the RX_ABORT and RX_DIS and clear it only after
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* RXE is set for MAC. This prevents frames with
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* corrupted descriptor status.
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*/
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REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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/*
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* For AR9280 and above, there is a new feature that allows
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* Multicast search based on both MAC Address and Key ID. By default,
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* this feature is enabled. But since the driver is not using this
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* feature, we switch it off; otherwise multicast search based on
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* MAC addr only will fail.
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*/
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val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
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REG_WRITE(ah, AR_PCU_MISC_MODE2,
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val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
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}
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static void ar9003_hw_prog_ini(struct ath_hw *ah,
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struct ar5416IniArray *iniArr,
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int column)
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{
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unsigned int i, regWrites = 0;
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/* New INI format: Array may be undefined (pre, core, post arrays) */
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if (!iniArr->ia_array)
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return;
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/*
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* New INI format: Pre, core, and post arrays for a given subsystem
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* may be modal (> 2 columns) or non-modal (2 columns). Determine if
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* the array is non-modal and force the column to 1.
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*/
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if (column >= iniArr->ia_columns)
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column = 1;
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for (i = 0; i < iniArr->ia_rows; i++) {
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u32 reg = INI_RA(iniArr, i, 0);
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u32 val = INI_RA(iniArr, i, column);
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REG_WRITE(ah, reg, val);
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/*
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* Determine if this is a shift register value, and insert the
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* configured delay if so.
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*/
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if (reg >= 0x16000 && reg < 0x17000
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&& ah->config.analog_shiftreg)
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udelay(100);
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DO_DELAY(regWrites);
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}
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}
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static int ar9003_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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/* TODO */
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return -1;
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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unsigned int regWrites = 0, i;
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struct ieee80211_channel *channel = chan->chan;
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u32 modesIndex, freqIndex;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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modesIndex = 1;
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freqIndex = 1;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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modesIndex = 2;
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freqIndex = 1;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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modesIndex = 4;
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freqIndex = 2;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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modesIndex = 3;
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freqIndex = 2;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
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ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
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ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
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ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
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ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
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}
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REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
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REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
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/*
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* For 5GHz channels requiring Fast Clock, apply
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* different modal values.
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*/
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if (IS_CHAN_A_5MHZ_SPACED(chan))
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REG_WRITE_ARRAY(&ah->iniModesAdditional,
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modesIndex, regWrites);
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ar9003_hw_override_ini(ah);
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ar9003_hw_set_channel_regs(ah, chan);
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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/* Set TX power */
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ah->eep_ops->set_txpower(ah, chan,
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ath9k_regd_get_ctl(regulatory, chan),
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channel->max_antenna_gain * 2,
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channel->max_power * 2,
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min((u32) MAX_RATE_POWER,
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(u32) regulatory->power_limit));
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return 0;
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}
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static void ar9003_hw_set_rfmode(struct ath_hw *ah,
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@ -801,4 +801,6 @@
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#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
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void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
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#endif /* AR9003_PHY_H */
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@ -1756,4 +1756,17 @@ enum {
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#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
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#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
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#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
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#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
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* based on both MAC Address and Key ID.
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* If bit is 0, then Multicast search is
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* based on MAC address only.
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* For Merlin and above only.
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*/
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#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
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* when it is enable, AGG_WEP would takes
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* charge of the encryption interface of
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* pcu_txsm.
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*/
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#endif
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