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x86/mce/AMD: Read MSRs on the CPU allocating the threshold blocks
Scalable MCA systems allow non-core MCA banks to only be accessible by certain CPUs. The MSRs for these banks are Read-as-Zero on other CPUs. During allocate_threshold_blocks(), get_block_address() can be scheduled on CPUs other than the one allocating the block. This causes the MSRs to be read on the wrong CPU and results in incorrect behavior. Add a @cpu parameter to get_block_address() and pass this in to ensure that the MSRs are only read on the CPU that is allocating the block. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1472673994-12235-2-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -293,7 +293,7 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
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wrmsr(MSR_CU_DEF_ERR, low, high);
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}
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static u32 get_block_address(u32 current_addr, u32 low, u32 high,
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static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
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unsigned int bank, unsigned int block)
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{
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u32 addr = 0, offset = 0;
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@ -309,13 +309,13 @@ static u32 get_block_address(u32 current_addr, u32 low, u32 high,
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*/
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u32 low, high;
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if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
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if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
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return addr;
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if (!(low & MCI_CONFIG_MCAX))
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return addr;
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if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
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if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
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(low & MASK_BLKPTR_LO))
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addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
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}
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@ -421,12 +421,12 @@ out:
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void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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u32 low = 0, high = 0, address = 0;
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unsigned int bank, block;
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unsigned int bank, block, cpu = smp_processor_id();
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int offset = -1;
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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for (block = 0; block < NR_BLOCKS; ++block) {
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address = get_block_address(address, low, high, bank, block);
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address = get_block_address(cpu, address, low, high, bank, block);
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if (!address)
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break;
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@ -544,15 +544,14 @@ static void amd_deferred_error_interrupt(void)
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static void amd_threshold_interrupt(void)
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{
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u32 low = 0, high = 0, address = 0;
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int cpu = smp_processor_id();
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unsigned int bank, block;
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unsigned int bank, block, cpu = smp_processor_id();
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/* assume first bank caused it */
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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if (!(per_cpu(bank_map, cpu) & (1 << bank)))
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continue;
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for (block = 0; block < NR_BLOCKS; ++block) {
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address = get_block_address(address, low, high, bank, block);
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address = get_block_address(cpu, address, low, high, bank, block);
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if (!address)
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break;
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@ -774,7 +773,7 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
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if (err)
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goto out_free;
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recurse:
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address = get_block_address(address, low, high, bank, ++block);
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address = get_block_address(cpu, address, low, high, bank, ++block);
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if (!address)
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return 0;
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