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drm/i915/gen9: fix watermarks when using the pipe scaler

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Luckily, the necessary adjustments for when we're using the scaler are
exactly the same as the ones needed on ILK+, so just reuse the
function we already have.

v2: Invert the patch order so stable backports get easier.

Cc: stable@vger.kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com
This commit is contained in:
Paulo Zanoni 2016-10-07 17:28:57 -03:00
parent c89cadd50b
commit cfd7e3a202
1 changed files with 3 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/i915/intel_pm.c
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@ -3498,12 +3498,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0; return 0;
} }
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
{
/* TODO: Take into account the scalers once we support them */
return config->base.adjusted_mode.crtc_clock;
}
/* /*
* The max latency should be 257 (max the punit can code is 255 and we add 2us * The max latency should be 257 (max the punit can code is 255 and we add 2us
* for the read latency) and cpp should always be <= 8, so that * for the read latency) and cpp should always be <= 8, so that
@ -3554,7 +3548,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
* Adjusted plane pixel rate is just the pipe's adjusted pixel rate * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
* with additional adjustments for plane-specific scaling. * with additional adjustments for plane-specific scaling.
*/ */
adjusted_pixel_rate = skl_pipe_pixel_rate(cstate); adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
downscale_amount = skl_plane_downscale_amount(pstate); downscale_amount = skl_plane_downscale_amount(pstate);
pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
@ -3763,11 +3757,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
if (!cstate->base.active) if (!cstate->base.active)
return 0; return 0;
if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
return 0; return 0;
return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
skl_pipe_pixel_rate(cstate)); ilk_pipe_pixel_rate(cstate));
} }
static void skl_compute_transition_wm(struct intel_crtc_state *cstate, static void skl_compute_transition_wm(struct intel_crtc_state *cstate,