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drm/nouveau/fifo/gf1xx: convert to using nvkm_fault_data
Would like to be able to reuse gf100_fifo_intr_fault() for (some of) the later chipsets too, as it's identical. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
9f9b450752
commit
cf9518b50a
@ -28,6 +28,7 @@
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#include <core/enum.h>
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#include <core/gpuobj.h>
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#include <subdev/bar.h>
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#include <subdev/fault.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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@ -193,6 +194,119 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
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nvkm_fifo_kevent(&fifo->base, chid);
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}
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static const struct nvkm_enum
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gf100_fifo_fault_engine[] = {
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{ 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
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{ 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
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{ 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
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{ 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
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{ 0x13, "PCOUNTER" },
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{ 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
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{ 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 },
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{ 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 },
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{ 0x17, "PMU" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_reason[] = {
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{ 0x00, "PT_NOT_PRESENT" },
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{ 0x01, "PT_TOO_SHORT" },
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{ 0x02, "PAGE_NOT_PRESENT" },
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{ 0x03, "VM_LIMIT_EXCEEDED" },
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{ 0x04, "NO_CHANNEL" },
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{ 0x05, "PAGE_SYSTEM_ONLY" },
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{ 0x06, "PAGE_READ_ONLY" },
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{ 0x0a, "COMPRESSED_SYSRAM" },
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{ 0x0c, "INVALID_STORAGE_TYPE" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_hubclient[] = {
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{ 0x01, "PCOPY0" },
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{ 0x02, "PCOPY1" },
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{ 0x04, "DISPATCH" },
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{ 0x05, "CTXCTL" },
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{ 0x06, "PFIFO" },
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{ 0x07, "BAR_READ" },
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{ 0x08, "BAR_WRITE" },
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{ 0x0b, "PVP" },
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{ 0x0c, "PMSPPP" },
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{ 0x0d, "PMSVLD" },
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{ 0x11, "PCOUNTER" },
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{ 0x12, "PMU" },
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{ 0x14, "CCACHE" },
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{ 0x15, "CCACHE_POST" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_gpcclient[] = {
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{ 0x01, "TEX" },
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{ 0x0c, "ESETUP" },
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{ 0x0e, "CTXCTL" },
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{ 0x0f, "PROP" },
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{}
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};
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static void
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gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
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{
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struct gf100_fifo *fifo = gf100_fifo(base);
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const struct nvkm_enum *er, *eu, *ec;
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struct nvkm_engine *engine = NULL;
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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char gpcid[8] = "";
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er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason);
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eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine);
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if (info->hub) {
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ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client);
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} else {
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ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client);
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snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc);
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}
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if (eu && eu->data2) {
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switch (eu->data2) {
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case NVKM_SUBDEV_BAR:
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nvkm_bar_bar1_reset(device);
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break;
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case NVKM_SUBDEV_INSTMEM:
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nvkm_bar_bar2_reset(device);
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break;
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case NVKM_ENGINE_IFB:
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nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
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break;
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default:
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engine = nvkm_device_engine(device, eu->data2);
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break;
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}
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}
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chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags);
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nvkm_error(subdev,
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"%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
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"reason %02x [%s] on channel %d [%010llx %s]\n",
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info->access ? "write" : "read", info->addr,
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info->engine, eu ? eu->name : "",
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info->client, gpcid, ec ? ec->name : "",
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info->reason, er ? er->name : "", chan ? chan->chid : -1,
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info->inst, chan ? chan->object.client->name : "unknown");
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if (engine && chan)
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gf100_fifo_recover(fifo, engine, (void *)chan);
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nvkm_fifo_chan_put(&fifo->base, flags, &chan);
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}
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static const struct nvkm_enum
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gf100_fifo_sched_reason[] = {
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{ 0x0a, "CTXSW_TIMEOUT" },
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@ -255,125 +369,28 @@ gf100_fifo_intr_sched(struct gf100_fifo *fifo)
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}
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}
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static const struct nvkm_enum
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gf100_fifo_fault_engine[] = {
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{ 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
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{ 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
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{ 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
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{ 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
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{ 0x13, "PCOUNTER" },
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{ 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
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{ 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 },
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{ 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 },
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{ 0x17, "PMU" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_reason[] = {
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{ 0x00, "PT_NOT_PRESENT" },
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{ 0x01, "PT_TOO_SHORT" },
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{ 0x02, "PAGE_NOT_PRESENT" },
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{ 0x03, "VM_LIMIT_EXCEEDED" },
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{ 0x04, "NO_CHANNEL" },
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{ 0x05, "PAGE_SYSTEM_ONLY" },
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{ 0x06, "PAGE_READ_ONLY" },
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{ 0x0a, "COMPRESSED_SYSRAM" },
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{ 0x0c, "INVALID_STORAGE_TYPE" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_hubclient[] = {
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{ 0x01, "PCOPY0" },
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{ 0x02, "PCOPY1" },
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{ 0x04, "DISPATCH" },
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{ 0x05, "CTXCTL" },
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{ 0x06, "PFIFO" },
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{ 0x07, "BAR_READ" },
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{ 0x08, "BAR_WRITE" },
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{ 0x0b, "PVP" },
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{ 0x0c, "PMSPPP" },
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{ 0x0d, "PMSVLD" },
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{ 0x11, "PCOUNTER" },
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{ 0x12, "PMU" },
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{ 0x14, "CCACHE" },
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{ 0x15, "CCACHE_POST" },
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{}
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};
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static const struct nvkm_enum
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gf100_fifo_fault_gpcclient[] = {
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{ 0x01, "TEX" },
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{ 0x0c, "ESETUP" },
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{ 0x0e, "CTXCTL" },
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{ 0x0f, "PROP" },
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{}
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};
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static void
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gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
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void
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gf100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_device *device = fifo->engine.subdev.device;
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u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
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u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
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u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
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u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
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u32 gpc = (stat & 0x1f000000) >> 24;
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u32 client = (stat & 0x00001f00) >> 8;
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u32 write = (stat & 0x00000080);
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u32 hub = (stat & 0x00000040);
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u32 reason = (stat & 0x0000000f);
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const struct nvkm_enum *er, *eu, *ec;
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struct nvkm_engine *engine = NULL;
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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char gpcid[8] = "";
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u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
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struct nvkm_fault_data info;
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er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
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eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
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if (hub) {
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ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
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} else {
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ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
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snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
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}
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info.inst = (u64)inst << 12;
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info.addr = ((u64)vahi << 32) | valo;
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info.time = 0;
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info.engine = unit;
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info.valid = 1;
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info.gpc = (type & 0x1f000000) >> 24;
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info.client = (type & 0x00001f00) >> 8;
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info.access = (type & 0x00000080) >> 7;
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info.hub = (type & 0x00000040) >> 6;
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info.reason = (type & 0x0000000f);
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if (eu && eu->data2) {
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switch (eu->data2) {
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case NVKM_SUBDEV_BAR:
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nvkm_bar_bar1_reset(device);
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break;
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case NVKM_SUBDEV_INSTMEM:
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nvkm_bar_bar2_reset(device);
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break;
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case NVKM_ENGINE_IFB:
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nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
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break;
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default:
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engine = nvkm_device_engine(device, eu->data2);
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break;
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}
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}
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chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags);
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nvkm_error(subdev,
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"%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
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"reason %02x [%s] on channel %d [%010llx %s]\n",
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write ? "write" : "read", (u64)vahi << 32 | valo,
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unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
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reason, er ? er->name : "", chan ? chan->chid : -1,
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(u64)inst << 12,
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chan ? chan->object.client->name : "unknown");
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if (engine && chan)
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gf100_fifo_recover(fifo, engine, (void *)chan);
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nvkm_fifo_chan_put(&fifo->base, flags, &chan);
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nvkm_fifo_fault(fifo, &info);
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}
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static const struct nvkm_bitfield
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@ -518,7 +535,7 @@ gf100_fifo_intr(struct nvkm_fifo *base)
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u32 mask = nvkm_rd32(device, 0x00259c);
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while (mask) {
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u32 unit = __ffs(mask);
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gf100_fifo_intr_fault(fifo, unit);
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gf100_fifo_intr_fault(&fifo->base, unit);
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nvkm_wr32(device, 0x00259c, (1 << unit));
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mask &= ~(1 << unit);
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}
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@ -655,6 +672,7 @@ gf100_fifo = {
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.init = gf100_fifo_init,
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.fini = gf100_fifo_fini,
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.intr = gf100_fifo_intr,
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.fault = gf100_fifo_fault,
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.uevent_init = gf100_fifo_uevent_init,
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.uevent_fini = gf100_fifo_uevent_fini,
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.chan = {
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@ -666,7 +666,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
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info.client = (type & 0x00001f00) >> 8;
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info.access = (type & 0x00000080) >> 7;
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info.hub = (type & 0x00000040) >> 6;
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info.reason = (type & 0x000000ff);
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info.reason = (type & 0x0000001f);
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nvkm_fifo_fault(&fifo->base, &info);
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}
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@ -37,4 +37,6 @@ struct nvkm_fifo_func {
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void nv04_fifo_intr(struct nvkm_fifo *);
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void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
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void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
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void gf100_fifo_intr_fault(struct nvkm_fifo *, int);
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#endif
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