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crypto: cavium/nitrox - Enabled Mailbox support
Enabled the PF->VF Mailbox support. Mailbox message are interpreted
as {type, opcode, data}. Supported message types are REQ, ACK and NACK.
Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Srikanth, Jampala
Herbert Xu
parent
19c11c97c3
commit
cf718eaa8f
@ -6,7 +6,8 @@ n5pf-objs := nitrox_main.o \
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nitrox_lib.o \
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nitrox_hal.o \
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nitrox_reqmgr.o \
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nitrox_algs.o
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nitrox_algs.o \
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nitrox_mbx.o
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n5pf-$(CONFIG_PCI_IOV) += nitrox_sriov.o
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n5pf-$(CONFIG_DEBUG_FS) += nitrox_debugfs.o
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@ -54,7 +54,13 @@
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#define NPS_STATS_PKT_DMA_WR_CNT 0x1000190
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/* NPS packet registers */
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#define NPS_PKT_INT 0x1040018
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#define NPS_PKT_INT 0x1040018
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#define NPS_PKT_MBOX_INT_LO 0x1040020
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#define NPS_PKT_MBOX_INT_LO_ENA_W1C 0x1040030
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#define NPS_PKT_MBOX_INT_LO_ENA_W1S 0x1040038
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#define NPS_PKT_MBOX_INT_HI 0x1040040
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#define NPS_PKT_MBOX_INT_HI_ENA_W1C 0x1040050
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#define NPS_PKT_MBOX_INT_HI_ENA_W1S 0x1040058
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#define NPS_PKT_IN_RERR_HI 0x1040108
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#define NPS_PKT_IN_RERR_HI_ENA_W1S 0x1040120
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#define NPS_PKT_IN_RERR_LO 0x1040128
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@ -74,6 +80,10 @@
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#define NPS_PKT_SLC_RERR_LO_ENA_W1S 0x1040240
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#define NPS_PKT_SLC_ERR_TYPE 0x1040248
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#define NPS_PKT_SLC_ERR_TYPE_ENA_W1S 0x1040260
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/* Mailbox PF->VF PF Accessible Data registers */
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#define NPS_PKT_MBOX_PF_VF_PFDATAX(_i) (0x1040800 + ((_i) * 0x8))
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#define NPS_PKT_MBOX_VF_PF_PFDATAX(_i) (0x1040C00 + ((_i) * 0x8))
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#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000))
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#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000))
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#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000))
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22
drivers/crypto/cavium/nitrox/nitrox_debugfs.h
Normal file
22
drivers/crypto/cavium/nitrox/nitrox_debugfs.h
Normal file
@ -0,0 +1,22 @@
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// SPDX-License-Identifier: GPL-2.0
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#ifndef __NITROX_DEBUGFS_H
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#define __NITROX_DEBUGFS_H
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#include "nitrox_dev.h"
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#ifdef CONFIG_DEBUG_FS
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int nitrox_debugfs_init(struct nitrox_device *ndev);
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void nitrox_debugfs_exit(struct nitrox_device *ndev);
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#else
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static inline int nitrox_debugfs_init(struct nitrox_device *ndev)
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{
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return 0;
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}
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static inline int nitrox_sriov_debugfs_init(struct nitrox_device *ndev)
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{
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return 0;
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}
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#endif /* !CONFIG_DEBUG_FS */
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#endif /* __NITROX_DEBUGFS_H */
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@ -8,6 +8,8 @@
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#include <linux/if.h>
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#define VERSION_LEN 32
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/* Maximum queues in PF mode */
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#define MAX_PF_QUEUES 64
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/**
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* struct nitrox_cmdq - NITROX command queue
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@ -103,13 +105,58 @@ struct nitrox_q_vector {
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};
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};
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/**
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* mbox_msg - Mailbox message data
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* @type: message type
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* @opcode: message opcode
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* @data: message data
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*/
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union mbox_msg {
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u64 value;
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struct {
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u64 type: 2;
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u64 opcode: 6;
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u64 data: 58;
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};
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struct {
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u64 type: 2;
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u64 opcode: 6;
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u64 chipid: 8;
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u64 vfid: 8;
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} id;
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};
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/**
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* nitrox_vfdev - NITROX VF device instance in PF
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* @state: VF device state
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* @vfno: VF number
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* @nr_queues: number of queues enabled in VF
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* @ring: ring to communicate with VF
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* @msg: Mailbox message data from VF
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* @mbx_resp: Mailbox counters
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*/
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struct nitrox_vfdev {
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atomic_t state;
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int vfno;
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int nr_queues;
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int ring;
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union mbox_msg msg;
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atomic64_t mbx_resp;
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};
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/**
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* struct nitrox_iov - SR-IOV information
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* @num_vfs: number of VF(s) enabled
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* @msix: MSI-X for PF in SR-IOV case
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* @max_vf_queues: Maximum number of queues allowed for VF
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* @vfdev: VF(s) devices
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* @pf2vf_wq: workqueue for PF2VF communication
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* @msix: MSI-X entry for PF in SR-IOV case
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*/
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struct nitrox_iov {
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int num_vfs;
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int max_vf_queues;
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struct nitrox_vfdev *vfdev;
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struct workqueue_struct *pf2vf_wq;
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struct msix_entry msix;
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};
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@ -226,17 +273,9 @@ static inline bool nitrox_ready(struct nitrox_device *ndev)
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return atomic_read(&ndev->state) == __NDEV_READY;
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}
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#ifdef CONFIG_DEBUG_FS
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int nitrox_debugfs_init(struct nitrox_device *ndev);
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void nitrox_debugfs_exit(struct nitrox_device *ndev);
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#else
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static inline int nitrox_debugfs_init(struct nitrox_device *ndev)
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static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev)
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{
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return 0;
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return atomic_read(&vfdev->state) == __NDEV_READY;
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}
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static inline void nitrox_debugfs_exit(struct nitrox_device *ndev)
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{ }
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#endif
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#endif /* __NITROX_DEV_H */
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@ -5,10 +5,11 @@
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#include "nitrox_csr.h"
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#define PLL_REF_CLK 50
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#define MAX_CSR_RETRIES 10
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/**
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* emu_enable_cores - Enable EMU cluster cores.
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* @ndev: N5 device
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* @ndev: NITROX device
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*/
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static void emu_enable_cores(struct nitrox_device *ndev)
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{
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@ -33,7 +34,7 @@ static void emu_enable_cores(struct nitrox_device *ndev)
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/**
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* nitrox_config_emu_unit - configure EMU unit.
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* @ndev: N5 device
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* @ndev: NITROX device
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*/
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void nitrox_config_emu_unit(struct nitrox_device *ndev)
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{
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@ -63,29 +64,26 @@ void nitrox_config_emu_unit(struct nitrox_device *ndev)
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static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
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union nps_pkt_in_done_cnts pkt_in_cnts;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* step 1: disable the ring, clear enable bit */
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offset = NPS_PKT_IN_INSTR_CTLX(ring);
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/* disable the ring */
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_in_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
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usleep_range(100, 150);
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/* wait to clear [ENB] */
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/* step 2: wait to clear [ENB] */
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usleep_range(100, 150);
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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} while (pkt_in_ctl.s.enb);
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if (!pkt_in_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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/* clear off door bell counts */
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offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(ring);
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pkt_in_dbell.value = 0;
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pkt_in_dbell.s.dbell = 0xffffffff;
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nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
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/* clear done counts */
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/* step 3: clear done counts */
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offset = NPS_PKT_IN_DONE_CNTSX(ring);
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pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
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@ -95,6 +93,7 @@ static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
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void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
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{
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union nps_pkt_in_instr_ctl pkt_in_ctl;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* 64-byte instruction size */
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@ -107,12 +106,15 @@ void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
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/* wait for set [ENB] */
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do {
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pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
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} while (!pkt_in_ctl.s.enb);
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if (pkt_in_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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}
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/**
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* nitrox_config_pkt_input_rings - configure Packet Input Rings
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* @ndev: N5 device
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* @ndev: NITROX device
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*/
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void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
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{
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@ -121,11 +123,14 @@ void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
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for (i = 0; i < ndev->nr_queues; i++) {
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struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
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union nps_pkt_in_instr_rsize pkt_in_rsize;
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union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
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u64 offset;
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reset_pkt_input_ring(ndev, i);
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/* configure ring base address 16-byte aligned,
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/**
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* step 4:
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* configure ring base address 16-byte aligned,
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* size and interrupt threshold.
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*/
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offset = NPS_PKT_IN_INSTR_BADDRX(i);
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@ -141,6 +146,13 @@ void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
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offset = NPS_PKT_IN_INT_LEVELSX(i);
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nitrox_write_csr(ndev, offset, 0xffffffff);
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/* step 5: clear off door bell counts */
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offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
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pkt_in_dbell.value = 0;
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pkt_in_dbell.s.dbell = 0xffffffff;
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nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
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/* enable the ring */
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enable_pkt_input_ring(ndev, i);
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}
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}
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@ -149,21 +161,26 @@ static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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union nps_pkt_slc_cnts pkt_slc_cnts;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* disable slc port */
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/* step 1: disable slc port */
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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pkt_slc_ctl.s.enb = 0;
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nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
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usleep_range(100, 150);
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/* step 2 */
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usleep_range(100, 150);
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/* wait to clear [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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} while (pkt_slc_ctl.s.enb);
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if (!pkt_slc_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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/* clear slc counters */
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/* step 3: clear slc counters */
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offset = NPS_PKT_SLC_CNTSX(port);
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pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
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nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
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@ -173,12 +190,12 @@ static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
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void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_ctl pkt_slc_ctl;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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offset = NPS_PKT_SLC_CTLX(port);
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pkt_slc_ctl.value = 0;
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pkt_slc_ctl.s.enb = 1;
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/*
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* 8 trailing 0x00 bytes will be added
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* to the end of the outgoing packet.
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@ -191,23 +208,27 @@ void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
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/* wait to set [ENB] */
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do {
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pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
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} while (!pkt_slc_ctl.s.enb);
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if (pkt_slc_ctl.s.enb)
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break;
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udelay(50);
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} while (max_retries--);
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}
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static void config_single_pkt_solicit_port(struct nitrox_device *ndev,
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int port)
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static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
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{
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union nps_pkt_slc_int_levels pkt_slc_int;
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u64 offset;
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reset_pkt_solicit_port(ndev, port);
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/* step 4: configure interrupt levels */
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offset = NPS_PKT_SLC_INT_LEVELSX(port);
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pkt_slc_int.value = 0;
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/* time interrupt threshold */
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pkt_slc_int.s.timet = 0x3fffff;
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nitrox_write_csr(ndev, offset, pkt_slc_int.value);
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/* enable the solicit port */
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enable_pkt_solicit_port(ndev, port);
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}
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@ -216,12 +237,12 @@ void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
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int i;
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for (i = 0; i < ndev->nr_queues; i++)
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config_single_pkt_solicit_port(ndev, i);
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config_pkt_solicit_port(ndev, i);
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}
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/**
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* enable_nps_interrupts - enable NPS interrutps
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* @ndev: N5 device.
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* @ndev: NITROX device.
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*
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* This includes NPS core, packet in and slc interrupts.
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*/
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@ -284,8 +305,8 @@ void nitrox_config_pom_unit(struct nitrox_device *ndev)
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}
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/**
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* nitrox_config_rand_unit - enable N5 random number unit
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* @ndev: N5 device
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* nitrox_config_rand_unit - enable NITROX random number unit
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* @ndev: NITROX device
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*/
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void nitrox_config_rand_unit(struct nitrox_device *ndev)
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{
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@ -361,6 +382,7 @@ void invalidate_lbc(struct nitrox_device *ndev)
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{
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union lbc_inval_ctl lbc_ctl;
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union lbc_inval_status lbc_stat;
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int max_retries = MAX_CSR_RETRIES;
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u64 offset;
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/* invalidate LBC */
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@ -370,10 +392,12 @@ void invalidate_lbc(struct nitrox_device *ndev)
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nitrox_write_csr(ndev, offset, lbc_ctl.value);
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offset = LBC_INVAL_STATUS;
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do {
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lbc_stat.value = nitrox_read_csr(ndev, offset);
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} while (!lbc_stat.s.done);
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if (lbc_stat.s.done)
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break;
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udelay(50);
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} while (max_retries--);
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}
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void nitrox_config_lbc_unit(struct nitrox_device *ndev)
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@ -467,3 +491,31 @@ void nitrox_get_hwinfo(struct nitrox_device *ndev)
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/* copy partname */
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strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
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}
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void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
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{
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u64 value = ~0ULL;
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u64 reg_addr;
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/* Mailbox interrupt low enable set register */
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reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1S;
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nitrox_write_csr(ndev, reg_addr, value);
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/* Mailbox interrupt high enable set register */
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reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1S;
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nitrox_write_csr(ndev, reg_addr, value);
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}
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|
||||
void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
|
||||
{
|
||||
u64 value = ~0ULL;
|
||||
u64 reg_addr;
|
||||
|
||||
/* Mailbox interrupt low enable clear register */
|
||||
reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1C;
|
||||
nitrox_write_csr(ndev, reg_addr, value);
|
||||
|
||||
/* Mailbox interrupt high enable clear register */
|
||||
reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1C;
|
||||
nitrox_write_csr(ndev, reg_addr, value);
|
||||
}
|
||||
|
||||
@ -19,5 +19,7 @@ void enable_pkt_input_ring(struct nitrox_device *ndev, int ring);
|
||||
void enable_pkt_solicit_port(struct nitrox_device *ndev, int port);
|
||||
void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode);
|
||||
void nitrox_get_hwinfo(struct nitrox_device *ndev);
|
||||
void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev);
|
||||
void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev);
|
||||
|
||||
#endif /* __NITROX_HAL_H */
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
#include "nitrox_csr.h"
|
||||
#include "nitrox_common.h"
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_mbx.h"
|
||||
|
||||
/**
|
||||
* One vector for each type of ring
|
||||
@ -220,7 +221,8 @@ static void nps_core_int_tasklet(unsigned long data)
|
||||
*/
|
||||
static irqreturn_t nps_core_int_isr(int irq, void *data)
|
||||
{
|
||||
struct nitrox_device *ndev = data;
|
||||
struct nitrox_q_vector *qvec = data;
|
||||
struct nitrox_device *ndev = qvec->ndev;
|
||||
union nps_core_int_active core_int;
|
||||
|
||||
core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
|
||||
@ -246,6 +248,10 @@ static irqreturn_t nps_core_int_isr(int irq, void *data)
|
||||
if (core_int.s.bmi)
|
||||
clear_bmi_err_intr(ndev);
|
||||
|
||||
/* Mailbox interrupt */
|
||||
if (core_int.s.mbox)
|
||||
nitrox_pf2vf_mbox_handler(ndev);
|
||||
|
||||
/* If more work callback the ISR, set resend */
|
||||
core_int.s.resend = 1;
|
||||
nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value);
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
#include <linux/aer.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
@ -13,9 +12,9 @@
|
||||
#include "nitrox_csr.h"
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_isr.h"
|
||||
#include "nitrox_debugfs.h"
|
||||
|
||||
#define CNN55XX_DEV_ID 0x12
|
||||
#define MAX_PF_QUEUES 64
|
||||
#define UCODE_HLEN 48
|
||||
#define SE_GROUP 0
|
||||
|
||||
|
||||
204
drivers/crypto/cavium/nitrox/nitrox_mbx.c
Normal file
204
drivers/crypto/cavium/nitrox/nitrox_mbx.c
Normal file
@ -0,0 +1,204 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "nitrox_csr.h"
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_dev.h"
|
||||
|
||||
#define RING_TO_VFNO(_x, _y) ((_x) / (_y))
|
||||
|
||||
/**
|
||||
* mbx_msg_type - Mailbox message types
|
||||
*/
|
||||
enum mbx_msg_type {
|
||||
MBX_MSG_TYPE_NOP,
|
||||
MBX_MSG_TYPE_REQ,
|
||||
MBX_MSG_TYPE_ACK,
|
||||
MBX_MSG_TYPE_NACK,
|
||||
};
|
||||
|
||||
/**
|
||||
* mbx_msg_opcode - Mailbox message opcodes
|
||||
*/
|
||||
enum mbx_msg_opcode {
|
||||
MSG_OP_VF_MODE = 1,
|
||||
MSG_OP_VF_UP,
|
||||
MSG_OP_VF_DOWN,
|
||||
MSG_OP_CHIPID_VFID,
|
||||
};
|
||||
|
||||
struct pf2vf_work {
|
||||
struct nitrox_vfdev *vfdev;
|
||||
struct nitrox_device *ndev;
|
||||
struct work_struct pf2vf_resp;
|
||||
};
|
||||
|
||||
static inline u64 pf2vf_read_mbox(struct nitrox_device *ndev, int ring)
|
||||
{
|
||||
u64 reg_addr;
|
||||
|
||||
reg_addr = NPS_PKT_MBOX_VF_PF_PFDATAX(ring);
|
||||
return nitrox_read_csr(ndev, reg_addr);
|
||||
}
|
||||
|
||||
static inline void pf2vf_write_mbox(struct nitrox_device *ndev, u64 value,
|
||||
int ring)
|
||||
{
|
||||
u64 reg_addr;
|
||||
|
||||
reg_addr = NPS_PKT_MBOX_PF_VF_PFDATAX(ring);
|
||||
nitrox_write_csr(ndev, reg_addr, value);
|
||||
}
|
||||
|
||||
static void pf2vf_send_response(struct nitrox_device *ndev,
|
||||
struct nitrox_vfdev *vfdev)
|
||||
{
|
||||
union mbox_msg msg;
|
||||
|
||||
msg.value = vfdev->msg.value;
|
||||
|
||||
switch (vfdev->msg.opcode) {
|
||||
case MSG_OP_VF_MODE:
|
||||
msg.data = ndev->mode;
|
||||
break;
|
||||
case MSG_OP_VF_UP:
|
||||
vfdev->nr_queues = vfdev->msg.data;
|
||||
atomic_set(&vfdev->state, __NDEV_READY);
|
||||
break;
|
||||
case MSG_OP_CHIPID_VFID:
|
||||
msg.id.chipid = ndev->idx;
|
||||
msg.id.vfid = vfdev->vfno;
|
||||
break;
|
||||
case MSG_OP_VF_DOWN:
|
||||
vfdev->nr_queues = 0;
|
||||
atomic_set(&vfdev->state, __NDEV_NOT_READY);
|
||||
break;
|
||||
default:
|
||||
msg.type = MBX_MSG_TYPE_NOP;
|
||||
break;
|
||||
}
|
||||
|
||||
if (msg.type == MBX_MSG_TYPE_NOP)
|
||||
return;
|
||||
|
||||
/* send ACK to VF */
|
||||
msg.type = MBX_MSG_TYPE_ACK;
|
||||
pf2vf_write_mbox(ndev, msg.value, vfdev->ring);
|
||||
|
||||
vfdev->msg.value = 0;
|
||||
atomic64_inc(&vfdev->mbx_resp);
|
||||
}
|
||||
|
||||
static void pf2vf_resp_handler(struct work_struct *work)
|
||||
{
|
||||
struct pf2vf_work *pf2vf_resp = container_of(work, struct pf2vf_work,
|
||||
pf2vf_resp);
|
||||
struct nitrox_vfdev *vfdev = pf2vf_resp->vfdev;
|
||||
struct nitrox_device *ndev = pf2vf_resp->ndev;
|
||||
|
||||
switch (vfdev->msg.type) {
|
||||
case MBX_MSG_TYPE_REQ:
|
||||
/* process the request from VF */
|
||||
pf2vf_send_response(ndev, vfdev);
|
||||
break;
|
||||
case MBX_MSG_TYPE_ACK:
|
||||
case MBX_MSG_TYPE_NACK:
|
||||
break;
|
||||
};
|
||||
|
||||
kfree(pf2vf_resp);
|
||||
}
|
||||
|
||||
void nitrox_pf2vf_mbox_handler(struct nitrox_device *ndev)
|
||||
{
|
||||
struct nitrox_vfdev *vfdev;
|
||||
struct pf2vf_work *pfwork;
|
||||
u64 value, reg_addr;
|
||||
u32 i;
|
||||
int vfno;
|
||||
|
||||
/* loop for VF(0..63) */
|
||||
reg_addr = NPS_PKT_MBOX_INT_LO;
|
||||
value = nitrox_read_csr(ndev, reg_addr);
|
||||
for_each_set_bit(i, (const unsigned long *)&value, BITS_PER_LONG) {
|
||||
/* get the vfno from ring */
|
||||
vfno = RING_TO_VFNO(i, ndev->iov.max_vf_queues);
|
||||
vfdev = ndev->iov.vfdev + vfno;
|
||||
vfdev->ring = i;
|
||||
/* fill the vf mailbox data */
|
||||
vfdev->msg.value = pf2vf_read_mbox(ndev, vfdev->ring);
|
||||
pfwork = kzalloc(sizeof(*pfwork), GFP_ATOMIC);
|
||||
if (!pfwork)
|
||||
continue;
|
||||
|
||||
pfwork->vfdev = vfdev;
|
||||
pfwork->ndev = ndev;
|
||||
INIT_WORK(&pfwork->pf2vf_resp, pf2vf_resp_handler);
|
||||
queue_work(ndev->iov.pf2vf_wq, &pfwork->pf2vf_resp);
|
||||
/* clear the corresponding vf bit */
|
||||
nitrox_write_csr(ndev, reg_addr, BIT_ULL(i));
|
||||
}
|
||||
|
||||
/* loop for VF(64..127) */
|
||||
reg_addr = NPS_PKT_MBOX_INT_HI;
|
||||
value = nitrox_read_csr(ndev, reg_addr);
|
||||
for_each_set_bit(i, (const unsigned long *)&value, BITS_PER_LONG) {
|
||||
/* get the vfno from ring */
|
||||
vfno = RING_TO_VFNO(i + 64, ndev->iov.max_vf_queues);
|
||||
vfdev = ndev->iov.vfdev + vfno;
|
||||
vfdev->ring = (i + 64);
|
||||
/* fill the vf mailbox data */
|
||||
vfdev->msg.value = pf2vf_read_mbox(ndev, vfdev->ring);
|
||||
|
||||
pfwork = kzalloc(sizeof(*pfwork), GFP_ATOMIC);
|
||||
if (!pfwork)
|
||||
continue;
|
||||
|
||||
pfwork->vfdev = vfdev;
|
||||
pfwork->ndev = ndev;
|
||||
INIT_WORK(&pfwork->pf2vf_resp, pf2vf_resp_handler);
|
||||
queue_work(ndev->iov.pf2vf_wq, &pfwork->pf2vf_resp);
|
||||
/* clear the corresponding vf bit */
|
||||
nitrox_write_csr(ndev, reg_addr, BIT_ULL(i));
|
||||
}
|
||||
}
|
||||
|
||||
int nitrox_mbox_init(struct nitrox_device *ndev)
|
||||
{
|
||||
struct nitrox_vfdev *vfdev;
|
||||
int i;
|
||||
|
||||
ndev->iov.vfdev = kcalloc(ndev->iov.num_vfs,
|
||||
sizeof(struct nitrox_vfdev), GFP_KERNEL);
|
||||
if (!ndev->iov.vfdev)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ndev->iov.num_vfs; i++) {
|
||||
vfdev = ndev->iov.vfdev + i;
|
||||
vfdev->vfno = i;
|
||||
}
|
||||
|
||||
/* allocate pf2vf response workqueue */
|
||||
ndev->iov.pf2vf_wq = alloc_workqueue("nitrox_pf2vf", 0, 0);
|
||||
if (!ndev->iov.pf2vf_wq) {
|
||||
kfree(ndev->iov.vfdev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* enable pf2vf mailbox interrupts */
|
||||
enable_pf2vf_mbox_interrupts(ndev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void nitrox_mbox_cleanup(struct nitrox_device *ndev)
|
||||
{
|
||||
/* disable pf2vf mailbox interrupts */
|
||||
disable_pf2vf_mbox_interrupts(ndev);
|
||||
/* destroy workqueue */
|
||||
if (ndev->iov.pf2vf_wq)
|
||||
destroy_workqueue(ndev->iov.pf2vf_wq);
|
||||
|
||||
kfree(ndev->iov.vfdev);
|
||||
ndev->iov.pf2vf_wq = NULL;
|
||||
ndev->iov.vfdev = NULL;
|
||||
}
|
||||
9
drivers/crypto/cavium/nitrox/nitrox_mbx.h
Normal file
9
drivers/crypto/cavium/nitrox/nitrox_mbx.h
Normal file
@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#ifndef __NITROX_MBX_H
|
||||
#define __NITROX_MBX_H
|
||||
|
||||
int nitrox_mbox_init(struct nitrox_device *ndev);
|
||||
void nitrox_mbox_cleanup(struct nitrox_device *ndev);
|
||||
void nitrox_pf2vf_mbox_handler(struct nitrox_device *ndev);
|
||||
|
||||
#endif /* __NITROX_MBX_H */
|
||||
@ -6,6 +6,7 @@
|
||||
#include "nitrox_hal.h"
|
||||
#include "nitrox_common.h"
|
||||
#include "nitrox_isr.h"
|
||||
#include "nitrox_mbx.h"
|
||||
|
||||
/**
|
||||
* num_vfs_valid - validate VF count
|
||||
@ -52,6 +53,31 @@ static inline enum vf_mode num_vfs_to_mode(int num_vfs)
|
||||
return mode;
|
||||
}
|
||||
|
||||
static inline int vf_mode_to_nr_queues(enum vf_mode mode)
|
||||
{
|
||||
int nr_queues = 0;
|
||||
|
||||
switch (mode) {
|
||||
case __NDEV_MODE_PF:
|
||||
nr_queues = MAX_PF_QUEUES;
|
||||
break;
|
||||
case __NDEV_MODE_VF16:
|
||||
nr_queues = 8;
|
||||
break;
|
||||
case __NDEV_MODE_VF32:
|
||||
nr_queues = 4;
|
||||
break;
|
||||
case __NDEV_MODE_VF64:
|
||||
nr_queues = 2;
|
||||
break;
|
||||
case __NDEV_MODE_VF128:
|
||||
nr_queues = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
return nr_queues;
|
||||
}
|
||||
|
||||
static void nitrox_pf_cleanup(struct nitrox_device *ndev)
|
||||
{
|
||||
/* PF has no queues in SR-IOV mode */
|
||||
@ -94,16 +120,31 @@ static int nitrox_pf_reinit(struct nitrox_device *ndev)
|
||||
return nitrox_crypto_register();
|
||||
}
|
||||
|
||||
static int nitrox_sriov_init(struct nitrox_device *ndev)
|
||||
{
|
||||
/* register interrupts for PF in SR-IOV */
|
||||
return nitrox_sriov_register_interupts(ndev);
|
||||
}
|
||||
|
||||
static void nitrox_sriov_cleanup(struct nitrox_device *ndev)
|
||||
{
|
||||
/* unregister interrupts for PF in SR-IOV */
|
||||
nitrox_sriov_unregister_interrupts(ndev);
|
||||
nitrox_mbox_cleanup(ndev);
|
||||
}
|
||||
|
||||
static int nitrox_sriov_init(struct nitrox_device *ndev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* register interrupts for PF in SR-IOV */
|
||||
ret = nitrox_sriov_register_interupts(ndev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nitrox_mbox_init(ndev);
|
||||
if (ret)
|
||||
goto sriov_init_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
sriov_init_fail:
|
||||
nitrox_sriov_cleanup(ndev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nitrox_sriov_enable(struct pci_dev *pdev, int num_vfs)
|
||||
@ -126,8 +167,9 @@ static int nitrox_sriov_enable(struct pci_dev *pdev, int num_vfs)
|
||||
}
|
||||
dev_info(DEV(ndev), "Enabled VF(s) %d\n", num_vfs);
|
||||
|
||||
ndev->iov.num_vfs = num_vfs;
|
||||
ndev->mode = num_vfs_to_mode(num_vfs);
|
||||
ndev->iov.num_vfs = num_vfs;
|
||||
ndev->iov.max_vf_queues = vf_mode_to_nr_queues(ndev->mode);
|
||||
/* set bit in flags */
|
||||
set_bit(__NDEV_SRIOV_BIT, &ndev->flags);
|
||||
|
||||
@ -169,6 +211,7 @@ static int nitrox_sriov_disable(struct pci_dev *pdev)
|
||||
clear_bit(__NDEV_SRIOV_BIT, &ndev->flags);
|
||||
|
||||
ndev->iov.num_vfs = 0;
|
||||
ndev->iov.max_vf_queues = 0;
|
||||
ndev->mode = __NDEV_MODE_PF;
|
||||
|
||||
/* cleanup PF SR-IOV resources */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user