drm/i915: Invert the mask and val arguments in wa_add() and WA_REG()

While trying to unify the order of those arguments throughout the
driver, Daniel noticed what we were inverting them in this part of the
code.

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Damien Lespiau 2014-12-08 17:35:37 +00:00 committed by Jani Nikula
parent 98533251b0
commit cf4b0de6a3

View File

@ -701,7 +701,7 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
}
static int wa_add(struct drm_i915_private *dev_priv,
const u32 addr, const u32 val, const u32 mask)
const u32 addr, const u32 mask, const u32 val)
{
const u32 idx = dev_priv->workarounds.count;
@ -717,25 +717,25 @@ static int wa_add(struct drm_i915_private *dev_priv,
return 0;
}
#define WA_REG(addr, val, mask) { \
const int r = wa_add(dev_priv, (addr), (val), (mask)); \
#define WA_REG(addr, mask, val) { \
const int r = wa_add(dev_priv, (addr), (mask), (val)); \
if (r) \
return r; \
}
#define WA_SET_BIT_MASKED(addr, mask) \
WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
WA_REG(addr, (mask) & 0xffff, _MASKED_BIT_ENABLE(mask))
#define WA_CLR_BIT_MASKED(addr, mask) \
WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
WA_REG(addr, (mask) & 0xffff, _MASKED_BIT_DISABLE(mask))
#define WA_SET_FIELD_MASKED(addr, mask, value) \
WA_REG(addr, _MASKED_FIELD(mask, value), mask)
WA_REG(addr, mask, _MASKED_FIELD(mask, value))
#define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
#define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
#define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
static int bdw_init_workarounds(struct intel_engine_cs *ring)
{