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arm64: dts: ls1028a: Fix incorrect I2C clock divider
Ls1028a platform, the i2c input clock is actually platform pll CLK / 4 (this is the hardware connection), other clock divider can not get the correct i2c clock, resulting in the output of SCL pin clock is not accurate. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -173,7 +173,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -183,7 +183,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -193,7 +193,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -203,7 +203,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -213,7 +213,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2040000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -223,7 +223,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2050000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -233,7 +233,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2060000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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@ -243,7 +243,7 @@
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#size-cells = <0>;
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reg = <0x0 0x2070000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 1>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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