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Qualcomm driver updates for 5.12
The socinfo driver gains support for dumping information about the platform's PMICs, as well as new definitions for a number of platforms. The LLCC driver gains SM8250 support, AOSS QMP gains SM8350 support and the RPMPD driver gains support for MSM8994 power domains. In addition to this it contains a few minor fixes in the ocmem, rpmh and llcc drivers. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmAbg1wbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FYYEP/R2zxLPj1ntJmyLV/MWX bioEGJWXKk60b2k5lAai2nwD/iswPqMyRtI3eXub7YVoYPRVMDHVl7nuGE83hHES r3OUCTisiM5VCOIYjzs9ZJJx4ceGzicsXoV2eEZUabQ4pg2/VHzdbh3DmH+Yh7hL PTgEiAYqQRSpRlFTf7ByccuqjAMyhs1GJ3Ajrl9dACsXIrT8ktPqk1UZ6JDl7w+3 iox86p6EzpcnzgMY1APNgAoMDqHNOMbZky5zvgWEdMXGnpBZGjY8l1XXzIG9ZjE2 o9u9DnxnCyBJoaxqbsBeHmFux2QCNTggQc4k5fd4BI0vFLR5X4sTyhcG2rEy12st LUaSKP9hb4M4JTkbMCvKAgae1FrMArLXAExhsoXopa2QwV0JwbtlE1onaOE4hsGT 9YmBuJD6auegplIroGbOEihoNrOhPWEiNCX8N9I0daPewY/ulzxqn57Blq1RVXmV xs3ifBVyiFTbTD/cFvyDKnLDbgPuaT1bUReG6QHZYzOO/vzshe6JkduNY/RRgRd/ l/ENBkZ70yQRvImIcbzRgmq767u7zGa7VWrwTmLOe8+5VxxosxZD1sYBioO9N2uL pZ5kfAeEAfhn70SX+12SMYIMKxNuvVSCesQNNoBHyMAQX6Y0pbuAyEEyrRdcgodO lT1qpN+V2lkjlmzWEiokI3V0 =rWBX -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for 5.12 The socinfo driver gains support for dumping information about the platform's PMICs, as well as new definitions for a number of platforms. The LLCC driver gains SM8250 support, AOSS QMP gains SM8350 support and the RPMPD driver gains support for MSM8994 power domains. In addition to this it contains a few minor fixes in the ocmem, rpmh and llcc drivers. * tag 'qcom-drivers-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: ocmem: don't return NULL in of_get_ocmem soc: qcom: socinfo: Remove unwanted le32_to_cpu() soc: qcom: aoss: Add SM8350 compatible drivers: soc: qcom: rpmpd: Add msm8994 RPM Power Domains soc: qcom: socinfo: Fix an off by one in qcom_show_pmic_model() soc: qcom: socinfo: Fix off-by-one array index bounds check soc: qcom: socinfo: Add MDM9607 IDs soc: qcom: socinfo: Add SoC IDs for APQ/MSM8998 soc: qcom: socinfo: Add SoC IDs for 630 family soc: qcom: socinfo: Open read access to all for debugfs soc: qcom: socinfo: add info from PMIC models array soc: qcom: socinfo: add several PMIC IDs soc: qcom: socinfo: add qrb5165 SoC ID soc: qcom: rpmh: Remove serialization of TCS commands soc: qcom: smem: use %*ph to print small buffer dt-bindings: soc: qcom: convert qcom,smem bindings to yaml drivers: qcom: rpmh-rsc: Do not read back the register write on trigger soc: qcom: llcc-qcom: Add support for SM8250 SoC soc: qcom: llcc-qcom: Extract major hardware version dt-bindings: msm: Add LLCC for SM8250 Link: https://lore.kernel.org/r/20210204052258.388890-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ce8ccf21c0
@ -24,6 +24,7 @@ properties:
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- qcom,sc7180-llcc
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- qcom,sdm845-llcc
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- qcom,sm8150-llcc
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- qcom,sm8250-llcc
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reg:
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items:
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@ -19,6 +19,7 @@ properties:
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- qcom,msm8916-rpmpd
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- qcom,msm8939-rpmpd
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- qcom,msm8976-rpmpd
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- qcom,msm8994-rpmpd
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- qcom,msm8996-rpmpd
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- qcom,msm8998-rpmpd
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- qcom,qcs404-rpmpd
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@ -20,6 +20,7 @@ power-domains.
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"qcom,sdm845-aoss-qmp"
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"qcom,sm8150-aoss-qmp"
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"qcom,sm8250-aoss-qmp"
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"qcom,sm8350-aoss-qmp"
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- reg:
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Usage: required
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@ -1,57 +0,0 @@
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Qualcomm Shared Memory Manager binding
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This binding describes the Qualcomm Shared Memory Manager, used to share data
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between various subsystems and OSes in Qualcomm platforms.
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: must be:
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"qcom,smem"
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- memory-region:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: handle to memory reservation for main SMEM memory region.
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- qcom,rpm-msg-ram:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: handle to RPM message memory resource
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- hwlocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to a hwspinlock used to protect allocations from
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the shared memory
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= EXAMPLE
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The following example shows the SMEM setup for MSM8974, with a main SMEM region
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at 0xfa00000 and the RPM message ram at 0xfc428000:
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_region: smem@fa00000 {
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reg = <0xfa00000 0x200000>;
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no-map;
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};
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};
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smem@fa00000 {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc {
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rpm_msg_ram: memory@fc428000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0xfc428000 0x4000>;
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};
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};
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72
Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml
Normal file
72
Documentation/devicetree/bindings/soc/qcom/qcom,smem.yaml
Normal file
@ -0,0 +1,72 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Shared Memory Manager binding
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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This binding describes the Qualcomm Shared Memory Manager, used to share data
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between various subsystems and OSes in Qualcomm platforms.
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properties:
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compatible:
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const: qcom,smem
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memory-region:
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maxItems: 1
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description: handle to memory reservation for main SMEM memory region.
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hwlocks:
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maxItems: 1
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qcom,rpm-msg-ram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: handle to RPM message memory resource
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required:
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- compatible
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- memory-region
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- hwlocks
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additionalProperties: false
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examples:
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- |
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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smem_region: smem@fa00000 {
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reg = <0xfa00000 0x200000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rpm_msg_ram: sram@fc428000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0xfc428000 0x4000>;
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};
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};
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...
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@ -4,6 +4,7 @@
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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@ -35,6 +36,9 @@
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#define CACHE_LINE_SIZE_SHIFT 6
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#define LLCC_COMMON_HW_INFO 0x00030000
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#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
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#define LLCC_COMMON_STATUS0 0x0003000c
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#define LLCC_LB_CNT_MASK GENMASK(31, 28)
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#define LLCC_LB_CNT_SHIFT 28
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@ -47,6 +51,7 @@
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#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
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#define LLCC_TRP_PCB_ACT 0x21f04
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#define LLCC_TRP_WRSC_EN 0x21f20
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#define BANK_OFFSET_STRIDE 0x80000
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@ -73,6 +78,7 @@
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* then the ways assigned to this client are not flushed on power
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* collapse.
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* @activate_on_init: Activate the slice immediately after it is programmed
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* @write_scid_en: Bit enables write cache support for a given scid.
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*/
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struct llcc_slice_config {
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u32 usecase_id;
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@ -87,6 +93,7 @@ struct llcc_slice_config {
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bool dis_cap_alloc;
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bool retain_on_pc;
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bool activate_on_init;
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bool write_scid_en;
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};
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struct qcom_llcc_config {
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@ -147,6 +154,25 @@ static const struct llcc_slice_config sm8150_data[] = {
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{ LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 },
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};
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static const struct llcc_slice_config sm8250_data[] = {
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{ LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 },
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{ LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
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{ LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 },
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{ LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 },
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{ LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
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{ LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
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{ LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 },
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{ LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
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};
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static const struct qcom_llcc_config sc7180_cfg = {
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.sct_data = sc7180_data,
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.size = ARRAY_SIZE(sc7180_data),
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@ -164,6 +190,11 @@ static const struct qcom_llcc_config sm8150_cfg = {
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.size = ARRAY_SIZE(sm8150_data),
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};
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static const struct qcom_llcc_config sm8250_cfg = {
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.sct_data = sm8250_data,
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.size = ARRAY_SIZE(sm8250_data),
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};
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static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
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/**
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@ -413,6 +444,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
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return ret;
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}
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if (drv_data->major_version == 2) {
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u32 wren;
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wren = config->write_scid_en << config->slice_id;
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ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN,
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BIT(config->slice_id), wren);
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if (ret)
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return ret;
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}
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if (config->activate_on_init) {
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desc.slice_id = config->slice_id;
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ret = llcc_slice_activate(&desc);
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@ -476,6 +517,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
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const struct qcom_llcc_config *cfg;
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const struct llcc_slice_config *llcc_cfg;
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u32 sz;
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u32 version;
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drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
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if (!drv_data) {
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@ -496,6 +538,13 @@ static int qcom_llcc_probe(struct platform_device *pdev)
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goto err;
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}
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/* Extract major version of the IP */
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ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
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if (ret)
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goto err;
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drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
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ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
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&num_banks);
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if (ret)
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@ -559,6 +608,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
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{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
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{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
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{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
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{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
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{ }
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};
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@ -189,6 +189,7 @@ struct ocmem *of_get_ocmem(struct device *dev)
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{
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struct platform_device *pdev;
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struct device_node *devnode;
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struct ocmem *ocmem;
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devnode = of_parse_phandle(dev->of_node, "sram", 0);
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if (!devnode || !devnode->parent) {
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@ -202,7 +203,12 @@ struct ocmem *of_get_ocmem(struct device *dev)
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return ERR_PTR(-EPROBE_DEFER);
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}
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||||
|
||||
return platform_get_drvdata(pdev);
|
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ocmem = platform_get_drvdata(pdev);
|
||||
if (!ocmem) {
|
||||
dev_err(dev, "Cannot get ocmem\n");
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
return ocmem;
|
||||
}
|
||||
EXPORT_SYMBOL(of_get_ocmem);
|
||||
|
||||
|
||||
@ -600,6 +600,7 @@ static const struct of_device_id qmp_dt_match[] = {
|
||||
{ .compatible = "qcom,sdm845-aoss-qmp", },
|
||||
{ .compatible = "qcom,sm8150-aoss-qmp", },
|
||||
{ .compatible = "qcom,sm8250-aoss-qmp", },
|
||||
{ .compatible = "qcom,sm8350-aoss-qmp", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qmp_dt_match);
|
||||
|
||||
@ -231,10 +231,9 @@ static void tcs_invalidate(struct rsc_drv *drv, int type)
|
||||
if (bitmap_empty(tcs->slots, MAX_TCS_SLOTS))
|
||||
return;
|
||||
|
||||
for (m = tcs->offset; m < tcs->offset + tcs->num_tcs; m++) {
|
||||
for (m = tcs->offset; m < tcs->offset + tcs->num_tcs; m++)
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, m, 0);
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, m, 0);
|
||||
}
|
||||
|
||||
bitmap_zero(tcs->slots, MAX_TCS_SLOTS);
|
||||
}
|
||||
|
||||
@ -364,7 +363,7 @@ static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger)
|
||||
enable = TCS_AMC_MODE_ENABLE;
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable);
|
||||
enable |= TCS_AMC_MODE_TRIGGER;
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CONTROL, tcs_id, enable);
|
||||
write_tcs_reg(drv, RSC_DRV_CONTROL, tcs_id, enable);
|
||||
}
|
||||
}
|
||||
|
||||
@ -443,7 +442,6 @@ static irqreturn_t tcs_tx_done(int irq, void *p)
|
||||
skip:
|
||||
/* Reclaim the TCS */
|
||||
write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0);
|
||||
write_tcs_reg(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, i, 0);
|
||||
writel_relaxed(BIT(i), drv->tcs_base + RSC_DRV_IRQ_CLEAR);
|
||||
spin_lock(&drv->lock);
|
||||
clear_bit(i, drv->tcs_in_use);
|
||||
@ -476,23 +474,23 @@ skip:
|
||||
static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,
|
||||
const struct tcs_request *msg)
|
||||
{
|
||||
u32 msgid, cmd_msgid;
|
||||
u32 msgid;
|
||||
u32 cmd_msgid = CMD_MSGID_LEN | CMD_MSGID_WRITE;
|
||||
u32 cmd_enable = 0;
|
||||
u32 cmd_complete;
|
||||
struct tcs_cmd *cmd;
|
||||
int i, j;
|
||||
|
||||
cmd_msgid = CMD_MSGID_LEN;
|
||||
/* Convert all commands to RR when the request has wait_for_compl set */
|
||||
cmd_msgid |= msg->wait_for_compl ? CMD_MSGID_RESP_REQ : 0;
|
||||
cmd_msgid |= CMD_MSGID_WRITE;
|
||||
|
||||
cmd_complete = read_tcs_reg(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, tcs_id);
|
||||
|
||||
for (i = 0, j = cmd_id; i < msg->num_cmds; i++, j++) {
|
||||
cmd = &msg->cmds[i];
|
||||
cmd_enable |= BIT(j);
|
||||
cmd_complete |= cmd->wait << j;
|
||||
msgid = cmd_msgid;
|
||||
/*
|
||||
* Additionally, if the cmd->wait is set, make the command
|
||||
* response reqd even if the overall request was fire-n-forget.
|
||||
*/
|
||||
msgid |= cmd->wait ? CMD_MSGID_RESP_REQ : 0;
|
||||
|
||||
write_tcs_cmd(drv, RSC_DRV_CMD_MSGID, tcs_id, j, msgid);
|
||||
@ -501,7 +499,6 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,
|
||||
trace_rpmh_send_msg(drv, tcs_id, j, msgid, cmd);
|
||||
}
|
||||
|
||||
write_tcs_reg(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, tcs_id, cmd_complete);
|
||||
cmd_enable |= read_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id);
|
||||
write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id, cmd_enable);
|
||||
}
|
||||
@ -652,7 +649,6 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg)
|
||||
* cleaned from rpmh_flush() by invoking rpmh_rsc_invalidate()
|
||||
*/
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, tcs_id, 0);
|
||||
write_tcs_reg_sync(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, tcs_id, 0);
|
||||
enable_tcs_irq(drv, tcs_id, true);
|
||||
}
|
||||
spin_unlock_irqrestore(&drv->lock, flags);
|
||||
|
||||
@ -21,6 +21,8 @@
|
||||
* RPMPD_X is X encoded as a little-endian, lower-case, ASCII string */
|
||||
#define RPMPD_SMPA 0x61706d73
|
||||
#define RPMPD_LDOA 0x616f646c
|
||||
#define RPMPD_SMPB 0x62706d73
|
||||
#define RPMPD_LDOB 0x626f646c
|
||||
#define RPMPD_RWCX 0x78637772
|
||||
#define RPMPD_RWMX 0x786d7772
|
||||
#define RPMPD_RWLC 0x636c7772
|
||||
@ -184,6 +186,31 @@ static const struct rpmpd_desc msm8976_desc = {
|
||||
.max_state = RPM_SMD_LEVEL_TURBO_HIGH,
|
||||
};
|
||||
|
||||
/* msm8994 RPM Power domains */
|
||||
DEFINE_RPMPD_PAIR(msm8994, vddcx, vddcx_ao, SMPA, CORNER, 1);
|
||||
DEFINE_RPMPD_PAIR(msm8994, vddmx, vddmx_ao, SMPA, CORNER, 2);
|
||||
/* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */
|
||||
DEFINE_RPMPD_CORNER(msm8994, vddgfx, SMPB, 2);
|
||||
|
||||
DEFINE_RPMPD_VFC(msm8994, vddcx_vfc, SMPA, 1);
|
||||
DEFINE_RPMPD_VFC(msm8994, vddgfx_vfc, SMPB, 2);
|
||||
|
||||
static struct rpmpd *msm8994_rpmpds[] = {
|
||||
[MSM8994_VDDCX] = &msm8994_vddcx,
|
||||
[MSM8994_VDDCX_AO] = &msm8994_vddcx_ao,
|
||||
[MSM8994_VDDCX_VFC] = &msm8994_vddcx_vfc,
|
||||
[MSM8994_VDDMX] = &msm8994_vddmx,
|
||||
[MSM8994_VDDMX_AO] = &msm8994_vddmx_ao,
|
||||
[MSM8994_VDDGFX] = &msm8994_vddgfx,
|
||||
[MSM8994_VDDGFX_VFC] = &msm8994_vddgfx_vfc,
|
||||
};
|
||||
|
||||
static const struct rpmpd_desc msm8994_desc = {
|
||||
.rpmpds = msm8994_rpmpds,
|
||||
.num_pds = ARRAY_SIZE(msm8994_rpmpds),
|
||||
.max_state = MAX_CORNER_RPMPD_STATE,
|
||||
};
|
||||
|
||||
/* msm8996 RPM Power domains */
|
||||
DEFINE_RPMPD_PAIR(msm8996, vddcx, vddcx_ao, SMPA, CORNER, 1);
|
||||
DEFINE_RPMPD_PAIR(msm8996, vddmx, vddmx_ao, SMPA, CORNER, 2);
|
||||
@ -302,6 +329,7 @@ static const struct of_device_id rpmpd_match_table[] = {
|
||||
{ .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc },
|
||||
{ .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc },
|
||||
{ .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc },
|
||||
{ .compatible = "qcom,msm8994-rpmpd", .data = &msm8994_desc },
|
||||
{ .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc },
|
||||
{ .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc },
|
||||
{ .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc },
|
||||
|
||||
@ -732,9 +732,7 @@ qcom_smem_partition_header(struct qcom_smem *smem,
|
||||
header = smem->regions[0].virt_base + le32_to_cpu(entry->offset);
|
||||
|
||||
if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) {
|
||||
dev_err(smem->dev, "bad partition magic %02x %02x %02x %02x\n",
|
||||
header->magic[0], header->magic[1],
|
||||
header->magic[2], header->magic[3]);
|
||||
dev_err(smem->dev, "bad partition magic %4ph\n", header->magic);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
@ -15,6 +15,8 @@
|
||||
#include <linux/sys_soc.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/unaligned.h>
|
||||
|
||||
/*
|
||||
* SoC version type with major number in the upper 16 bits and minor
|
||||
* number in the lower 16 bits.
|
||||
@ -83,6 +85,11 @@ static const char *const pmic_models[] = {
|
||||
[23] = "PM8038",
|
||||
[24] = "PM8922",
|
||||
[25] = "PM8917",
|
||||
[30] = "PM8150",
|
||||
[31] = "PM8150L",
|
||||
[32] = "PM8150B",
|
||||
[33] = "PMK8002",
|
||||
[36] = "PM8009",
|
||||
};
|
||||
#endif /* CONFIG_DEBUG_FS */
|
||||
|
||||
@ -217,23 +224,39 @@ static const struct soc_id soc_id[] = {
|
||||
{ 250, "MSM8616" },
|
||||
{ 251, "MSM8992" },
|
||||
{ 253, "APQ8094" },
|
||||
{ 290, "MDM9607" },
|
||||
{ 291, "APQ8096" },
|
||||
{ 292, "MSM8998" },
|
||||
{ 293, "MSM8953" },
|
||||
{ 296, "MDM8207" },
|
||||
{ 297, "MDM9207" },
|
||||
{ 298, "MDM9307" },
|
||||
{ 299, "MDM9628" },
|
||||
{ 304, "APQ8053" },
|
||||
{ 305, "MSM8996SG" },
|
||||
{ 310, "MSM8996AU" },
|
||||
{ 311, "APQ8096AU" },
|
||||
{ 312, "APQ8096SG" },
|
||||
{ 317, "SDM660" },
|
||||
{ 318, "SDM630" },
|
||||
{ 319, "APQ8098" },
|
||||
{ 321, "SDM845" },
|
||||
{ 322, "MDM9206" },
|
||||
{ 324, "SDA660" },
|
||||
{ 325, "SDM658" },
|
||||
{ 326, "SDA658" },
|
||||
{ 327, "SDA630" },
|
||||
{ 338, "SDM450" },
|
||||
{ 341, "SDA845" },
|
||||
{ 345, "SDM636" },
|
||||
{ 346, "SDA636" },
|
||||
{ 349, "SDM632" },
|
||||
{ 350, "SDA632" },
|
||||
{ 351, "SDA450" },
|
||||
{ 356, "SM8250" },
|
||||
{ 402, "IPQ6018" },
|
||||
{ 425, "SC7180" },
|
||||
{ 455, "QRB5165" },
|
||||
};
|
||||
|
||||
static const char *socinfo_machine(struct device *dev, unsigned int id)
|
||||
@ -264,7 +287,7 @@ static const struct file_operations qcom_ ##name## _ops = { \
|
||||
}
|
||||
|
||||
#define DEBUGFS_ADD(info, name) \
|
||||
debugfs_create_file(__stringify(name), 0400, \
|
||||
debugfs_create_file(__stringify(name), 0444, \
|
||||
qcom_socinfo->dbg_root, \
|
||||
info, &qcom_ ##name## _ops)
|
||||
|
||||
@ -286,7 +309,7 @@ static int qcom_show_pmic_model(struct seq_file *seq, void *p)
|
||||
if (model < 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (model <= ARRAY_SIZE(pmic_models) && pmic_models[model])
|
||||
if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
|
||||
seq_printf(seq, "%s\n", pmic_models[model]);
|
||||
else
|
||||
seq_printf(seq, "unknown (%d)\n", model);
|
||||
@ -294,6 +317,32 @@ static int qcom_show_pmic_model(struct seq_file *seq, void *p)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
|
||||
{
|
||||
struct socinfo *socinfo = seq->private;
|
||||
unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
|
||||
unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
|
||||
int i;
|
||||
void *ptr = socinfo;
|
||||
|
||||
ptr += pmic_array_offset;
|
||||
|
||||
/* No need for bounds checking, it happened at socinfo_debugfs_init */
|
||||
for (i = 0; i < num_pmics; i++) {
|
||||
unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
|
||||
unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
|
||||
|
||||
if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
|
||||
seq_printf(seq, "%s %u.%u\n", pmic_models[model],
|
||||
SOCINFO_MAJOR(die_rev),
|
||||
SOCINFO_MINOR(die_rev));
|
||||
else
|
||||
seq_printf(seq, "unknown (%d)\n", model);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
|
||||
{
|
||||
struct socinfo *socinfo = seq->private;
|
||||
@ -316,6 +365,7 @@ static int qcom_show_chip_id(struct seq_file *seq, void *p)
|
||||
|
||||
QCOM_OPEN(build_id, qcom_show_build_id);
|
||||
QCOM_OPEN(pmic_model, qcom_show_pmic_model);
|
||||
QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
|
||||
QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
|
||||
QCOM_OPEN(chip_id, qcom_show_chip_id);
|
||||
|
||||
@ -344,25 +394,27 @@ DEFINE_IMAGE_OPS(variant);
|
||||
DEFINE_IMAGE_OPS(oem);
|
||||
|
||||
static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
struct socinfo *info)
|
||||
struct socinfo *info, size_t info_size)
|
||||
{
|
||||
struct smem_image_version *versions;
|
||||
struct dentry *dentry;
|
||||
size_t size;
|
||||
int i;
|
||||
unsigned int num_pmics;
|
||||
unsigned int pmic_array_offset;
|
||||
|
||||
qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
|
||||
|
||||
qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
|
||||
|
||||
debugfs_create_x32("info_fmt", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.fmt);
|
||||
|
||||
switch (qcom_socinfo->info.fmt) {
|
||||
case SOCINFO_VERSION(0, 15):
|
||||
qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
|
||||
|
||||
debugfs_create_u32("nmodem_supported", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.nmodem_supported);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 14):
|
||||
@ -371,19 +423,19 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
|
||||
qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
|
||||
|
||||
debugfs_create_u32("num_clusters", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.num_clusters);
|
||||
debugfs_create_u32("ncluster_array_offset", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.ncluster_array_offset);
|
||||
debugfs_create_u32("num_defective_parts", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.num_defective_parts);
|
||||
debugfs_create_u32("ndefective_parts_array_offset", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.ndefective_parts_array_offset);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 13):
|
||||
qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
|
||||
|
||||
debugfs_create_u32("nproduct_id", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.nproduct_id);
|
||||
DEBUGFS_ADD(info, chip_id);
|
||||
fallthrough;
|
||||
@ -395,21 +447,26 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
qcom_socinfo->info.raw_device_num =
|
||||
__le32_to_cpu(info->raw_device_num);
|
||||
|
||||
debugfs_create_x32("chip_family", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.chip_family);
|
||||
debugfs_create_x32("raw_device_family", 0400,
|
||||
debugfs_create_x32("raw_device_family", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.raw_device_family);
|
||||
debugfs_create_x32("raw_device_number", 0400,
|
||||
debugfs_create_x32("raw_device_number", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.raw_device_num);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 11):
|
||||
num_pmics = le32_to_cpu(info->num_pmics);
|
||||
pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
|
||||
if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
|
||||
DEBUGFS_ADD(info, pmic_model_array);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 10):
|
||||
case SOCINFO_VERSION(0, 9):
|
||||
qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
|
||||
|
||||
debugfs_create_u32("foundry_id", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.foundry_id);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 8):
|
||||
@ -421,7 +478,7 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
qcom_socinfo->info.hw_plat_subtype =
|
||||
__le32_to_cpu(info->hw_plat_subtype);
|
||||
|
||||
debugfs_create_u32("hardware_platform_subtype", 0400,
|
||||
debugfs_create_u32("hardware_platform_subtype", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.hw_plat_subtype);
|
||||
fallthrough;
|
||||
@ -429,28 +486,28 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
qcom_socinfo->info.accessory_chip =
|
||||
__le32_to_cpu(info->accessory_chip);
|
||||
|
||||
debugfs_create_u32("accessory_chip", 0400,
|
||||
debugfs_create_u32("accessory_chip", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.accessory_chip);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 4):
|
||||
qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
|
||||
|
||||
debugfs_create_u32("platform_version", 0400,
|
||||
debugfs_create_u32("platform_version", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.plat_ver);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 3):
|
||||
qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
|
||||
|
||||
debugfs_create_u32("hardware_platform", 0400,
|
||||
debugfs_create_u32("hardware_platform", 0444,
|
||||
qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.hw_plat);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 2):
|
||||
qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
|
||||
|
||||
debugfs_create_u32("raw_version", 0400, qcom_socinfo->dbg_root,
|
||||
debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
|
||||
&qcom_socinfo->info.raw_ver);
|
||||
fallthrough;
|
||||
case SOCINFO_VERSION(0, 1):
|
||||
@ -467,11 +524,11 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
|
||||
dentry = debugfs_create_dir(socinfo_image_names[i],
|
||||
qcom_socinfo->dbg_root);
|
||||
debugfs_create_file("name", 0400, dentry, &versions[i],
|
||||
debugfs_create_file("name", 0444, dentry, &versions[i],
|
||||
&qcom_image_name_ops);
|
||||
debugfs_create_file("variant", 0400, dentry, &versions[i],
|
||||
debugfs_create_file("variant", 0444, dentry, &versions[i],
|
||||
&qcom_image_variant_ops);
|
||||
debugfs_create_file("oem", 0400, dentry, &versions[i],
|
||||
debugfs_create_file("oem", 0444, dentry, &versions[i],
|
||||
&qcom_image_oem_ops);
|
||||
}
|
||||
}
|
||||
@ -482,7 +539,7 @@ static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
|
||||
}
|
||||
#else
|
||||
static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
||||
struct socinfo *info)
|
||||
struct socinfo *info, size_t info_size)
|
||||
{
|
||||
}
|
||||
static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
|
||||
@ -522,7 +579,7 @@ static int qcom_socinfo_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(qs->soc_dev))
|
||||
return PTR_ERR(qs->soc_dev);
|
||||
|
||||
socinfo_debugfs_init(qs, info);
|
||||
socinfo_debugfs_init(qs, info, item_size);
|
||||
|
||||
/* Feed the soc specific unique data into entropy pool */
|
||||
add_device_randomness(info, item_size);
|
||||
|
||||
@ -94,6 +94,15 @@
|
||||
#define MSM8976_VDDMX_AO 4
|
||||
#define MSM8976_VDDMX_VFL 5
|
||||
|
||||
/* MSM8994 Power Domain Indexes */
|
||||
#define MSM8994_VDDCX 0
|
||||
#define MSM8994_VDDCX_AO 1
|
||||
#define MSM8994_VDDCX_VFC 2
|
||||
#define MSM8994_VDDMX 3
|
||||
#define MSM8994_VDDMX_AO 4
|
||||
#define MSM8994_VDDGFX 5
|
||||
#define MSM8994_VDDGFX_VFC 6
|
||||
|
||||
/* MSM8996 Power Domain Indexes */
|
||||
#define MSM8996_VDDCX 0
|
||||
#define MSM8996_VDDCX_AO 1
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#define LLCC_AUDHW 22
|
||||
#define LLCC_NPU 23
|
||||
#define LLCC_WLHW 24
|
||||
#define LLCC_CVP 28
|
||||
#define LLCC_MODPE 29
|
||||
#define LLCC_APTCM 30
|
||||
#define LLCC_WRCACHE 31
|
||||
@ -79,6 +80,7 @@ struct llcc_edac_reg_data {
|
||||
* @bitmap: Bit map to track the active slice ids
|
||||
* @offsets: Pointer to the bank offsets array
|
||||
* @ecc_irq: interrupt for llcc cache error detection and reporting
|
||||
* @major_version: Indicates the LLCC major version
|
||||
*/
|
||||
struct llcc_drv_data {
|
||||
struct regmap *regmap;
|
||||
@ -91,6 +93,7 @@ struct llcc_drv_data {
|
||||
unsigned long *bitmap;
|
||||
u32 *offsets;
|
||||
int ecc_irq;
|
||||
u32 major_version;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_LLCC)
|
||||
|
||||
@ -30,7 +30,13 @@ enum rpmh_state {
|
||||
*
|
||||
* @addr: the address of the resource slv_id:18:16 | offset:0:15
|
||||
* @data: the resource state request
|
||||
* @wait: wait for this request to be complete before sending the next
|
||||
* @wait: ensure that this command is complete before returning.
|
||||
* Setting "wait" here only makes sense during rpmh_write_batch() for
|
||||
* active-only transfers, this is because:
|
||||
* rpmh_write() - Always waits.
|
||||
* (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
|
||||
* rpmh_write_async() - Never waits.
|
||||
* (There's no request completion callback)
|
||||
*/
|
||||
struct tcs_cmd {
|
||||
u32 addr;
|
||||
@ -43,6 +49,7 @@ struct tcs_cmd {
|
||||
*
|
||||
* @state: state for the request.
|
||||
* @wait_for_compl: wait until we get a response from the h/w accelerator
|
||||
* (same as setting cmd->wait for all commands in the request)
|
||||
* @num_cmds: the number of @cmds in this request
|
||||
* @cmds: an array of tcs_cmds
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user