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drm/i915/gt: Restore coarse power gating
The coarse power gating was disabled as part of commit2248a28384
("drm/i915/gen8+: Add RC6 CTX corruption WA") as a prelude to recover from the context corruption; the power gating itself has no direct impact on the RC6 context corruption. However, that recovery scheme was never implemented due to difficult corner cases, and so we no longer need to keep the power gating disabled. Fixes:2248a28384
("drm/i915/gen8+: Add RC6 CTX corruption WA") Closes: https://gitlab.freedesktop.org/drm/intel/issues/846 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Eero Tamminen <eero.t.tamminen@intel.com> Cc: Jon Bloomfield <jon.bloomfield@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191231122708.4025916-1-chris@chris-wilson.co.uk (cherry picked from commit32f408ac3e
) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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@ -1660,8 +1660,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
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/* WaRsDisableCoarsePowerGating:skl,cnl */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || \
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IS_SKL_GT3(dev_priv) || \
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IS_SKL_GT4(dev_priv))
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#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
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#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
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