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clk: imx8mq: add 27m phy pll ref clock

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According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225090002.2497057-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
This commit is contained in:
Peng Fan 2022-02-25 17:00:02 +08:00 committed by Abel Vesa
parent 3123109284
commit cdc86e473b
1 changed files with 1 additions and 1 deletions
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drivers/clk/imx/clk-imx8mq.c
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@ -25,7 +25,7 @@ static u32 share_count_sai6;
static u32 share_count_dcss;
static u32 share_count_nand;
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };