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drm/i915: remove render reclock support

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This code generally fails to adjust the render clock, and when it does,
it conflicts with some other register settings and can cause problems.

So remove this code altogether.  I'm reworking it now to do the right
thing, but the only bit it will share is the VBT check for whether
reclocking is supported, so I'm leaving that bit.

Reverts most of 652c393a33 ("add dynamic
clock frequency control"), though for many the regressions showed up
in the later 181a5336d6 ("Fix render
reclock availability detection").

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes 2009-12-17 11:11:13 -08:00 committed by Eric Anholt
parent 1d3c36ad41
commit cda9d05c49
1 changed files with 2 additions and 130 deletions
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132
drivers/gpu/drm/i915/intel_display.c
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@ -3779,125 +3779,6 @@ static void intel_gpu_idle_timer(unsigned long arg)
queue_work(dev_priv->wq, &dev_priv->idle_work);
}
void intel_increase_renderclock(struct drm_device *dev, bool schedule)
{
drm_i915_private_t *dev_priv = dev->dev_private;
if (IS_IRONLAKE(dev))
return;
if (!dev_priv->render_reclock_avail) {
DRM_DEBUG_DRIVER("not reclocking render clock\n");
return;
}
/* Restore render clock frequency to original value */
if (IS_G4X(dev) || IS_I9XX(dev))
pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
else if (IS_I85X(dev))
pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
DRM_DEBUG_DRIVER("increasing render clock frequency\n");
/* Schedule downclock */
if (schedule)
mod_timer(&dev_priv->idle_timer, jiffies +
msecs_to_jiffies(GPU_IDLE_TIMEOUT));
}
void intel_decrease_renderclock(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
if (IS_IRONLAKE(dev))
return;
if (!dev_priv->render_reclock_avail) {
DRM_DEBUG_DRIVER("not reclocking render clock\n");
return;
}
if (IS_G4X(dev)) {
u16 gcfgc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
/* Down to minimum... */
gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
pci_write_config_word(dev->pdev, GCFGC, gcfgc);
} else if (IS_I965G(dev)) {
u16 gcfgc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
/* Down to minimum... */
gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
pci_write_config_word(dev->pdev, GCFGC, gcfgc);
} else if (IS_I945G(dev) || IS_I945GM(dev)) {
u16 gcfgc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
/* Down to minimum... */
gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
pci_write_config_word(dev->pdev, GCFGC, gcfgc);
} else if (IS_I915G(dev)) {
u16 gcfgc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
/* Down to minimum... */
gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
pci_write_config_word(dev->pdev, GCFGC, gcfgc);
} else if (IS_I85X(dev)) {
u16 hpllcc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
/* Up to maximum... */
hpllcc &= ~GC_CLOCK_CONTROL_MASK;
hpllcc |= GC_CLOCK_133_200;
pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
}
DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
}
/* Note that no increase function is needed for this - increase_renderclock()
* will also rewrite these bits
*/
void intel_decrease_displayclock(struct drm_device *dev)
{
if (IS_IRONLAKE(dev))
return;
if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
IS_I915GM(dev)) {
u16 gcfgc;
/* Adjust render clock... */
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
/* Down to minimum... */
gcfgc &= ~0xf0;
gcfgc |= 0x80;
pci_write_config_word(dev->pdev, GCFGC, gcfgc);
}
}
#define CRTC_IDLE_TIMEOUT 1000 /* ms */
static void intel_crtc_idle_timer(unsigned long arg)
@ -4011,12 +3892,6 @@ static void intel_idle_update(struct work_struct *work)
mutex_lock(&dev->struct_mutex);
/* GPU isn't processing, downclock it. */
if (!dev_priv->busy) {
intel_decrease_renderclock(dev);
intel_decrease_displayclock(dev);
}
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
/* Skip inactive CRTCs */
if (!crtc->fb)
@ -4050,13 +3925,11 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
if (!drm_core_check_feature(dev, DRIVER_MODESET))
return;
if (!dev_priv->busy) {
if (!dev_priv->busy)
dev_priv->busy = true;
intel_increase_renderclock(dev, true);
} else {
else
mod_timer(&dev_priv->idle_timer, jiffies +
msecs_to_jiffies(GPU_IDLE_TIMEOUT));
}
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
if (!crtc->fb)
@ -4784,7 +4657,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
del_timer_sync(&intel_crtc->idle_timer);
}
intel_increase_renderclock(dev, false);
del_timer_sync(&dev_priv->idle_timer);
if (dev_priv->display.disable_fbc)