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perf/x86: Remove pmu->pebs_no_xmm_regs
We don't need pmu->pebs_no_xmm_regs anymore, the capabilities PERF_PMU_CAP_EXTENDED_REGS can be used to check if XMM registers collection is supported. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: https://lkml.kernel.org/r/1559081314-9714-4-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -568,7 +568,7 @@ int x86_pmu_hw_config(struct perf_event *event)
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* be collected in PEBS on some platforms, e.g. Icelake
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*/
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if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
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if (x86_pmu.pebs_no_xmm_regs)
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if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
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return -EINVAL;
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if (!event->attr.precise_ip)
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@ -1964,10 +1964,9 @@ void __init intel_ds_init(void)
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x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
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x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
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x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
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if (x86_pmu.version <= 4) {
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if (x86_pmu.version <= 4)
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x86_pmu.pebs_no_isolation = 1;
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x86_pmu.pebs_no_xmm_regs = 1;
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}
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if (x86_pmu.pebs) {
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char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
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char *pebs_qual = "";
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@ -2023,7 +2022,6 @@ void __init intel_ds_init(void)
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x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
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} else {
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/* Only basic record supported */
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x86_pmu.pebs_no_xmm_regs = 1;
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x86_pmu.large_pebs_flags &=
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~(PERF_SAMPLE_ADDR |
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PERF_SAMPLE_TIME |
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@ -650,8 +650,7 @@ struct x86_pmu {
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pebs_broken :1,
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pebs_prec_dist :1,
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pebs_no_tlb :1,
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pebs_no_isolation :1,
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pebs_no_xmm_regs :1;
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pebs_no_isolation :1;
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int pebs_record_size;
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int pebs_buffer_size;
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int max_pebs_events;
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