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drm/amd/pp: Fix build warning in vegam
warning: missing braces around initializer [-Wmissing-braces] Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -320,7 +320,7 @@ int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
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pp_atomctrl_memory_clock_param_ai *mpll_param)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
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COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0};
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int result;
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mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
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@ -1366,10 +1366,12 @@ static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
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struct SMU75_Discrete_MCArbDramTimingTable arb_regs = {0};
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struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
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uint32_t i, j;
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int result = 0;
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memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
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for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
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for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
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result = vegam_populate_memory_timing_parameters(hwmgr,
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