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ASoC: SOF: Intel: hda-mlink: add helper to program SoundWire PCMSyCM registers
These registers enable the HDaudio DMA hardware to split/merge data from different PDIs, possibly on different links. This capability exists for all types of HDaudio extended links, but for now is only required for SoundWire. In the SSP/DMIC case, the IP is programmed by the DSP firmware. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com Reviewed-by: Rander Wang <rander.wang@intel.com Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com Link: https://lore.kernel.org/r/20230512174611.84372-7-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org
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@ -44,6 +44,9 @@ int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink);
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int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num);
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int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y,
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int channel_mask, int stream_id, int dir);
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void hda_bus_ml_put_all(struct hdac_bus *bus);
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void hda_bus_ml_reset_losidv(struct hdac_bus *bus);
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int hda_bus_ml_resume(struct hdac_bus *bus);
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@ -145,6 +148,13 @@ hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink) { return
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static inline int
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hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; }
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static inline int
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hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y,
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int channel_mask, int stream_id, int dir)
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{
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return 0;
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}
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static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { }
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static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { }
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static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; }
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@ -73,6 +73,7 @@ struct hdac_ext2_link {
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#define AZX_REG_SDW_SHIM_OFFSET 0x0
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#define AZX_REG_SDW_IP_OFFSET 0x100
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#define AZX_REG_SDW_VS_SHIM_OFFSET 0x6000
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#define AZX_REG_SDW_SHIM_PCMSyCM(y) (0x16 + 0x4 * (y))
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/* only one instance supported */
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#define AZX_REG_INTEL_DMIC_SHIM_OFFSET 0x0
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@ -340,6 +341,21 @@ static void hdaml_link_set_lsdiid(u32 __iomem *lsdiid, int dev_num)
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writel(val, lsdiid);
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}
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static void hdaml_shim_map_stream_ch(u16 __iomem *pcmsycm, int lchan, int hchan,
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int stream_id, int dir)
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{
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u16 val;
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val = readw(pcmsycm);
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u16p_replace_bits(&val, lchan, GENMASK(3, 0));
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u16p_replace_bits(&val, hchan, GENMASK(7, 4));
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u16p_replace_bits(&val, stream_id, GENMASK(13, 8));
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u16p_replace_bits(&val, dir, BIT(15));
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writew(val, pcmsycm);
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}
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static void hdaml_lctl_offload_enable(u32 __iomem *lctl, bool enable)
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{
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u32 val = readl(lctl);
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@ -756,6 +772,40 @@ int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num)
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return 0;
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} EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_set_lsdiid, SND_SOC_SOF_HDA_MLINK);
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/*
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* the 'y' parameter comes from the PCMSyCM hardware register naming. 'y' refers to the
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* PDI index, i.e. the FIFO used for RX or TX
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*/
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int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y,
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int channel_mask, int stream_id, int dir)
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{
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struct hdac_ext2_link *h2link;
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u16 __iomem *pcmsycm;
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u16 val;
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h2link = find_ext2_link(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
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if (!h2link)
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return -ENODEV;
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pcmsycm = h2link->base_ptr + h2link->shim_offset +
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h2link->instance_offset * sublink +
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AZX_REG_SDW_SHIM_PCMSyCM(y);
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mutex_lock(&h2link->eml_lock);
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hdaml_shim_map_stream_ch(pcmsycm, 0, hweight32(channel_mask),
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stream_id, dir);
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mutex_unlock(&h2link->eml_lock);
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val = readw(pcmsycm);
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dev_dbg(bus->dev, "channel_mask %#x stream_id %d dir %d pcmscm %#x\n",
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channel_mask, stream_id, dir, val);
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return 0;
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} EXPORT_SYMBOL_NS(hdac_bus_eml_sdw_map_stream_ch, SND_SOC_SOF_HDA_MLINK);
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void hda_bus_ml_put_all(struct hdac_bus *bus)
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{
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struct hdac_ext_link *hlink;
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