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ARM: dts: rockchip: add i2s nodes for RK322x SoCs
This patch add the i2s dt nodes for rk322x SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -138,6 +138,47 @@
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#clock-cells = <0>;
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};
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i2s1: i2s1@100b0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100b0000 0x4000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
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dmas = <&pdma 14>, <&pdma 15>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s0: i2s0@100c0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100c0000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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dmas = <&pdma 11>, <&pdma 12>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2s2: i2s2@100e0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100e0000 0x4000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
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dmas = <&pdma 0>, <&pdma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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grf: syscon@11000000 {
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compatible = "syscon";
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reg = <0x11000000 0x1000>;
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@ -507,6 +548,20 @@
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};
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};
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i2s1 {
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i2s1_bus: i2s1-bus {
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rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
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<0 9 RK_FUNC_1 &pcfg_pull_none>,
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<0 11 RK_FUNC_1 &pcfg_pull_none>,
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<0 12 RK_FUNC_1 &pcfg_pull_none>,
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<0 13 RK_FUNC_1 &pcfg_pull_none>,
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<0 14 RK_FUNC_1 &pcfg_pull_none>,
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<1 2 RK_FUNC_1 &pcfg_pull_none>,
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<1 4 RK_FUNC_1 &pcfg_pull_none>,
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<1 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
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