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[ARM] 4790/1: S3C2412: Fix parent selection for msysclk.

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The msysclk clock was checking for the wrong PLL for the
parent in s3c2412_setparent_msysclk(), trying the UPLL instead
of the MPLL output.

Also ensure the mpll and fclks are at the same rate at init time.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks 2008-01-28 13:01:30 +01:00 committed by Russell King
parent e95f52cd3b
commit cca851d7b4
2 changed files with 3 additions and 1 deletions
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2
arch/arm/mach-s3c2412/clock.c
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@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
if (parent == &clk_mdivclk)
clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
else if (parent == &clk_upll)
else if (parent == &clk_mpll)
clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
else
return -EINVAL;

2
arch/arm/mach-s3c2412/s3c2412.c
View File

@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal)
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
clk_mpll.rate = fclk;
tmp = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */