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ARM: SoC 64-bit changes and additions

Browse Source 
The 64-bit set of updates this release cycle adds support for three new platforms:
 
 - Samsunc Exynos 7
 - Freescale LS2085a
 - Mediatek MT8173
 
 For all these, the changes mostly consititude additions of DT contents,
 but also some Kconfig entries to allow dependency/selection of drivers
 per-platform, etc.
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Merge tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC 64-bit changes and additions from Olof Johansson:
 "The 64-bit set of updates this release cycle adds support for three
  new platforms:

   - Samsunc Exynos 7
   - Freescale LS2085a
   - Mediatek MT8173

  For all these, the changes mostly consititude additions of DT
  contents, but also some Kconfig entries to allow dependency/selection
  of drivers per-platform, etc"

* tag '64bit-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: Kconfig: clean up two no-op Kconfig options from CONFIG_ARCH_TEGRA*
  arm64: Fix sort of platform Kconfig entries
  arm64: Add support for FSL's LS2085A SoC in Kconfig and defconfig
  arm64: Add DTS support for FSL's LS2085A SoC
  arm64: mediatek: Add MT8173 SoC Kconfig and defconfig
  arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile
  Document: DT: Add bindings for mediatek MT8173 SoC Platform
  arm64: Add Tegra132 support
  arm64: Enable ARMv8 based exynos7 SoC support
  arm64: dts: Add nodes for mmc, i2c, rtc, watchdog, adc on exynos7
  arm64: dts: Add PMU DT node for exynos7 SoC
  arm64: dts: Add initial pinctrl support to exynos7
  arm64: dts: Add initial device tree support for exynos7
This commit is contained in:
Linus Torvalds 2015-02-17 09:47:46 -08:00
commit cc4f9c2a91
17 changed files with 1720 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/mediatek.txt
View File

@ -9,6 +9,7 @@ compatible: Must contain one of
"mediatek,mt6592"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
Supported boards:
@ -25,3 +26,6 @@ Supported boards:
- MTK mt8135 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
- MTK mt8173 tablet EVB:
Required root node properties:
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
View File

@ -5,6 +5,7 @@ interrupt.
Required properties:
- compatible: should be one of:
"mediatek,mt8173-sysirq"
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
"mediatek,mt6592-sysirq"

1
Documentation/devicetree/bindings/arm/samsung/pmu.txt
View File

@ -10,6 +10,7 @@ Properties:
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
- "samsung,exynos7-pmu" - for Exynos7 SoC.
second value must be always "syscon".
- reg : offset and length of the register set.

4
Documentation/devicetree/bindings/serial/mtk-uart.txt
View File

@ -4,9 +4,11 @@ Required properties:
- compatible should contain:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
MT6577)
- reg: The base address of the UART register bank.

54
arch/arm64/Kconfig
View File

@ -149,11 +149,65 @@ source "kernel/Kconfig.freezer"
menu "Platform selection"
config ARCH_EXYNOS
bool
help
This enables support for Samsung Exynos SoC family
config ARCH_EXYNOS7
bool "ARMv8 based Samsung Exynos7"
select ARCH_EXYNOS
select COMMON_CLK_SAMSUNG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
help
This enables support for Samsung Exynos7 SoC family
config ARCH_FSL_LS2085A
bool "Freescale LS2085A SOC"
help
This enables support for Freescale LS2085A SOC.
config ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
select ARM_GIC
help
Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
config ARCH_SEATTLE
bool "AMD Seattle SoC Family"
help
This enables support for AMD Seattle SOC Family
config ARCH_TEGRA
bool "NVIDIA Tegra SoC Family"
select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select PINCTRL
select RESET_CONTROLLER
help
This enables support for the NVIDIA Tegra SoC family.
config ARCH_TEGRA_132_SOC
bool "NVIDIA Tegra132 SoC"
depends on ARCH_TEGRA
select PINCTRL_TEGRA124
select USB_ULPI if USB_PHY
select USB_ULPI_VIEWPORT if USB_PHY
help
Enable support for NVIDIA Tegra132 SoC, based on the Denver
ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
but contains an NVIDIA Denver CPU complex in place of
Tegra124's "4+1" Cortex-A15 CPU complex.
config ARCH_THUNDER
bool "Cavium Inc. Thunder SoC Family"
help

3
arch/arm64/boot/dts/Makefile
View File

@ -2,5 +2,8 @@ dts-dirs += amd
dts-dirs += apm
dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
subdir-y := $(dts-dirs)

5
arch/arm64/boot/dts/exynos/Makefile Normal file
View File

@ -0,0 +1,5 @@
dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

84
arch/arm64/boot/dts/exynos/exynos7-espresso.dts Normal file
View File

@ -0,0 +1,84 @@
/*
* SAMSUNG Exynos7 Espresso board device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos7.dtsi"
/ {
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
compatible = "samsung,exynos7-espresso", "samsung,exynos7";
aliases {
serial0 = &serial_2;
mshc0 = &mmc_0;
mshc2 = &mmc_2;
};
chosen {
linux,stdout-path = &serial_2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0xC0000000>;
};
};
&fin_pll {
clock-frequency = <24000000>;
};
&serial_2 {
status = "okay";
};
&rtc {
status = "okay";
};
&watchdog {
status = "okay";
};
&adc {
status = "okay";
};
&mmc_0 {
status = "okay";
num-slots = <1>;
broken-cd;
cap-mmc-highspeed;
non-removable;
card-detect-delay = <200>;
clock-frequency = <800000000>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
};
&mmc_2 {
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
card-detect-delay = <200>;
clock-frequency = <400000000>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
disable-wp;
};

588
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi Normal file
View File

@ -0,0 +1,588 @@
/*
* Samsung's Exynos7 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
* device tree nodes in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl_alive {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa3: gpa3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_bus0 {
gpb0: gpb0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd2: gpd2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd4: gpd4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd5: gpd5 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd6: gpd6 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd7: gpd7 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd8: gpd8 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c10_bus: hs-i2c10-bus {
samsung,pins = "gpb0-1", "gpb0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c11_bus: hs-i2c11-bus {
samsung,pins = "gpb0-3", "gpb0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c2_bus: hs-i2c2-bus {
samsung,pins = "gpd0-3", "gpd0-2";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart0_data: uart0-data {
samsung,pins = "gpd0-0", "gpd0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpd0-2", "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpd1-4", "gpd1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
hs_i2c3_bus: hs-i2c3-bus {
samsung,pins = "gpd1-3", "gpd1-2";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpd1-0", "gpd1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpd1-2", "gpd1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
hs_i2c0_bus: hs-i2c0-bus {
samsung,pins = "gpd2-1", "gpd2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c1_bus: hs-i2c1-bus {
samsung,pins = "gpd2-3", "gpd2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c9_bus: hs-i2c9-bus {
samsung,pins = "gpd2-7", "gpd2-6";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd2-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
hs_i2c8_bus: hs-i2c8-bus {
samsung,pins = "gpd5-3", "gpd5-2";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart3_data: uart3-data {
samsung,pins = "gpd5-0", "gpd5-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c4_bus: hs-i2c4-bus {
samsung,pins = "gpg3-1", "gpg3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
hs_i2c5_bus: hs-i2c5-bus {
samsung,pins = "gpg3-3", "gpg3-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_nfc {
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c6_bus: hs-i2c6-bus {
samsung,pins = "gpj0-1", "gpj0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_touch {
gpj1: gpj1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hs_i2c7_bus: hs-i2c7-bus {
samsung,pins = "gpj1-1", "gpj1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_ff {
gpg4: gpg4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
spi3_bus: spi3-bus {
samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_ese {
gpv7: gpv7 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
spi4_bus: spi4-bus {
samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&pinctrl_fsys0 {
gpr4: gpr4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpr4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpr4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpr4-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpr4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
};
&pinctrl_fsys1 {
gpr0: gpr0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr1: gpr1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr2: gpr2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpr3: gpr3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpr0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpr0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_ds: sd0-ds {
samsung,pins = "gpr0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
};
sd0_qrdy: sd0-qrdy {
samsung,pins = "gpr0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpr1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpr2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpr2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <2>;
};
sd1_ds: sd1-ds {
samsung,pins = "gpr2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <6>;
};
sd1_qrdy: sd1-qrdy {
samsung,pins = "gpr2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <6>;
};
sd1_int: sd1-int {
samsung,pins = "gpr2-4";
samsung,pin-function = <2>;
samsung,pin-pud = <1>;
samsung,pin-drv = <6>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpr3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
sd1_bus8: sd1-bus-width8 {
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <2>;
};
};

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/*
* SAMSUNG EXYNOS7 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/exynos7-clk.h>
/ {
compatible = "samsung,exynos7";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_bus0;
pinctrl2 = &pinctrl_nfc;
pinctrl3 = &pinctrl_touch;
pinctrl4 = &pinctrl_ff;
pinctrl5 = &pinctrl_ese;
pinctrl6 = &pinctrl_fsys0;
pinctrl7 = &pinctrl_fsys1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x2>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x18000000>;
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
fin_pll: xxti {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
gic: interrupt-controller@11001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x11001000 0x1000>,
<0x11002000 0x1000>,
<0x11004000 0x2000>,
<0x11006000 0x2000>;
};
clock_topc: clock-controller@10570000 {
compatible = "samsung,exynos7-clock-topc";
reg = <0x10570000 0x10000>;
#clock-cells = <1>;
};
clock_top0: clock-controller@105d0000 {
compatible = "samsung,exynos7-clock-top0";
reg = <0x105d0000 0xb000>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
<&clock_topc DOUT_SCLK_MFC_PLL>;
clock-names = "fin_pll", "dout_sclk_bus0_pll",
"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
"dout_sclk_mfc_pll";
};
clock_top1: clock-controller@105e0000 {
compatible = "samsung,exynos7-clock-top1";
reg = <0x105e0000 0xb000>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
<&clock_topc DOUT_SCLK_MFC_PLL>;
clock-names = "fin_pll", "dout_sclk_bus0_pll",
"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
"dout_sclk_mfc_pll";
};
clock_ccore: clock-controller@105b0000 {
compatible = "samsung,exynos7-clock-ccore";
reg = <0x105b0000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
clock-names = "fin_pll", "dout_aclk_ccore_133";
};
clock_peric0: clock-controller@13610000 {
compatible = "samsung,exynos7-clock-peric0";
reg = <0x13610000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
<&clock_top0 CLK_SCLK_UART0>;
clock-names = "fin_pll", "dout_aclk_peric0_66",
"sclk_uart0";
};
clock_peric1: clock-controller@14c80000 {
compatible = "samsung,exynos7-clock-peric1";
reg = <0x14c80000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
<&clock_top0 CLK_SCLK_UART1>,
<&clock_top0 CLK_SCLK_UART2>,
<&clock_top0 CLK_SCLK_UART3>;
clock-names = "fin_pll", "dout_aclk_peric1_66",
"sclk_uart1", "sclk_uart2", "sclk_uart3";
};
clock_peris: clock-controller@10040000 {
compatible = "samsung,exynos7-clock-peris";
reg = <0x10040000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
clock-names = "fin_pll", "dout_aclk_peris_66";
};
clock_fsys0: clock-controller@10e90000 {
compatible = "samsung,exynos7-clock-fsys0";
reg = <0x10e90000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
<&clock_top1 DOUT_SCLK_MMC2>;
clock-names = "fin_pll", "dout_aclk_fsys0_200",
"dout_sclk_mmc2";
};
clock_fsys1: clock-controller@156e0000 {
compatible = "samsung,exynos7-clock-fsys1";
reg = <0x156e0000 0xd00>;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
<&clock_top1 DOUT_SCLK_MMC0>,
<&clock_top1 DOUT_SCLK_MMC1>;
clock-names = "fin_pll", "dout_aclk_fsys1_200",
"dout_sclk_mmc0", "dout_sclk_mmc1";
};
serial_0: serial@13630000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13630000 0x100>;
interrupts = <0 440 0>;
clocks = <&clock_peric0 PCLK_UART0>,
<&clock_peric0 SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
serial_1: serial@14c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c20000 0x100>;
interrupts = <0 456 0>;
clocks = <&clock_peric1 PCLK_UART1>,
<&clock_peric1 SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
serial_2: serial@14c30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c30000 0x100>;
interrupts = <0 457 0>;
clocks = <&clock_peric1 PCLK_UART2>,
<&clock_peric1 SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
serial_3: serial@14c40000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c40000 0x100>;
interrupts = <0 458 0>;
clocks = <&clock_peric1 PCLK_UART3>,
<&clock_peric1 SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
pinctrl_alive: pinctrl@10580000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x10580000 0x1000>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 16 0>;
};
};
pinctrl_bus0: pinctrl@13470000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x13470000 0x1000>;
interrupts = <0 383 0>;
};
pinctrl_nfc: pinctrl@14cd0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14cd0000 0x1000>;
interrupts = <0 473 0>;
};
pinctrl_touch: pinctrl@14ce0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ce0000 0x1000>;
interrupts = <0 474 0>;
};
pinctrl_ff: pinctrl@14c90000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14c90000 0x1000>;
interrupts = <0 475 0>;
};
pinctrl_ese: pinctrl@14ca0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ca0000 0x1000>;
interrupts = <0 476 0>;
};
pinctrl_fsys0: pinctrl@10e60000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x10e60000 0x1000>;
interrupts = <0 221 0>;
};
pinctrl_fsys1: pinctrl@15690000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x15690000 0x1000>;
interrupts = <0 203 0>;
};
hsi2c_0: hsi2c@13640000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13640000 0x1000>;
interrupts = <0 441 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c0_bus>;
clocks = <&clock_peric0 PCLK_HSI2C0>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_1: hsi2c@13650000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13650000 0x1000>;
interrupts = <0 442 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c1_bus>;
clocks = <&clock_peric0 PCLK_HSI2C1>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_2: hsi2c@14e60000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e60000 0x1000>;
interrupts = <0 459 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c2_bus>;
clocks = <&clock_peric1 PCLK_HSI2C2>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_3: hsi2c@14e70000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e70000 0x1000>;
interrupts = <0 460 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c3_bus>;
clocks = <&clock_peric1 PCLK_HSI2C3>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_4: hsi2c@13660000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13660000 0x1000>;
interrupts = <0 443 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c4_bus>;
clocks = <&clock_peric0 PCLK_HSI2C4>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_5: hsi2c@13670000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13670000 0x1000>;
interrupts = <0 444 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c5_bus>;
clocks = <&clock_peric0 PCLK_HSI2C5>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_6: hsi2c@14e00000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e00000 0x1000>;
interrupts = <0 461 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c6_bus>;
clocks = <&clock_peric1 PCLK_HSI2C6>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_7: hsi2c@13e10000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13e10000 0x1000>;
interrupts = <0 462 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c7_bus>;
clocks = <&clock_peric1 PCLK_HSI2C7>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_8: hsi2c@14e20000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e20000 0x1000>;
interrupts = <0 463 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c8_bus>;
clocks = <&clock_peric1 PCLK_HSI2C8>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_9: hsi2c@13680000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13680000 0x1000>;
interrupts = <0 445 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c9_bus>;
clocks = <&clock_peric0 PCLK_HSI2C9>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_10: hsi2c@13690000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13690000 0x1000>;
interrupts = <0 446 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c10_bus>;
clocks = <&clock_peric0 PCLK_HSI2C10>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_11: hsi2c@136a0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x136a0000 0x1000>;
interrupts = <0 447 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c11_bus>;
clocks = <&clock_peric0 PCLK_HSI2C11>;
clock-names = "hsi2c";
status = "disabled";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>,
<1 14 0xff01>,
<1 11 0xff01>,
<1 10 0xff01>;
};
pmu_system_controller: system-controller@105c0000 {
compatible = "samsung,exynos7-pmu", "syscon";
reg = <0x105c0000 0x5000>;
};
rtc: rtc@10590000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10590000 0x100>;
interrupts = <0 355 0>, <0 356 0>;
clocks = <&clock_ccore PCLK_RTC>;
clock-names = "rtc";
status = "disabled";
};
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x101d0000 0x100>;
interrupts = <0 110 0>;
clocks = <&clock_peris PCLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
mmc_0: mmc@15740000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <0 201 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15740000 0x2000>;
clocks = <&clock_fsys1 ACLK_MMC0>,
<&clock_top1 CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_1: mmc@15750000 {
compatible = "samsung,exynos7-dw-mshc";
interrupts = <0 202 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15750000 0x2000>;
clocks = <&clock_fsys1 ACLK_MMC1>,
<&clock_top1 CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_2: mmc@15560000 {
compatible = "samsung,exynos7-dw-mshc-smu";
interrupts = <0 216 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15560000 0x2000>;
clocks = <&clock_fsys0 ACLK_MMC2>,
<&clock_top1 CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
adc: adc@13620000 {
compatible = "samsung,exynos7-adc";
reg = <0x13620000 0x100>;
interrupts = <0 448 0>;
clocks = <&clock_peric0 PCLK_ADCIF>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
pwm: pwm@136c0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x136c0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
clocks = <&clock_peric0 PCLK_PWM>;
clock-names = "timers";
};
};
};
#include "exynos7-pinctrl.dtsi"

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dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

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/*
* Device Tree file for Freescale LS2085a software Simulator model
*
* Copyright (C) 2014, Freescale Semiconductor
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "fsl-ls2085a.dtsi"
/ {
model = "Freescale Layerscape 2085a software Simulator model";
compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
ethernet@2210000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x2210000 0x0 0x100>;
interrupts = <0 58 0x1>;
};
};

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/*
* Device Tree Include file for Freescale Layerscape-2085A family SoC.
*
* Copyright (C) 2014, Freescale Semiconductor
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
compatible = "fsl,ls2085a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
/*
* We expect the enable-method for cpu's to be "psci", but this
* is dependent on the SoC FW, which will fill this in.
*
* Currently supported enable-method is psci v0.2
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <1 9 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
<1 11 0x8>, /* Virtual PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clock-frequency = <0>; /* Updated by bootloader */
interrupts = <0 32 0x1>; /* edge triggered */
};
serial1: serial@21c0600 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clock-frequency = <0>; /* Updated by bootloader */
interrupts = <0 32 0x1>; /* edge triggered */
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};
};

5
arch/arm64/boot/dts/mediatek/Makefile Normal file
View File

@ -0,0 +1,5 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

38
arch/arm64/boot/dts/mediatek/mt8173-evb.dts Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Eddie Huang <eddie.huang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "mt8173.dtsi"
/ {
model = "mediatek,mt8173-evb";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
chosen { };
};
&uart0 {
status = "okay";
};

168
arch/arm64/boot/dts/mediatek/mt8173.dtsi Normal file
View File

@ -0,0 +1,168 @@
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Eddie Huang <eddie.huang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt8173";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu2>;
};
core1 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
enable-method = "psci";
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
gic: interrupt-controller@10220000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10221000 0 0x1000>,
<0 0x10222000 0 0x2000>,
<0 0x10224000 0 0x2000>,
<0 0x10226000 0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt8173-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
};
};

3
arch/arm64/configs/defconfig
View File

@ -31,6 +31,8 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_FSL_LS2085A=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_XGENE=y
@ -88,6 +90,7 @@ CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y