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gpio: ep93xx: split device in multiple
Prepare ep93xx SOC gpio to convert into device tree driver: - dropped banks and legacy defines - split AB IRQ and make it shared We are relying on IRQ number information A, B ports have single shared IRQ, while F port have dedicated IRQ for each line. Also we had to split single ep93xx platform_device into multiple, one for each port, without this we can't do a full working transition from legacy platform code into device tree capable. All GPIO_LOOKUP were change to match new chip namings. Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Nikita Shubin
Arnd Bergmann
parent
a8c39443a3
commit
cbe8e464eb
@ -35,6 +35,7 @@
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#include <linux/reboot.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <linux/random.h>
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#include <linux/ioport.h>
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#include "hardware.h"
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#include <linux/platform_data/video-ep93xx.h>
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@ -139,9 +140,80 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
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/*************************************************************************
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* EP93xx GPIO
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*************************************************************************/
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static struct resource ep93xx_gpio_resource[] = {
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DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
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/* port A */
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static struct resource ep93xx_a_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"),
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB),
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};
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static struct platform_device ep93xx_a_gpio = {
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.name = "gpio-ep93xx",
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.id = 0,
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.num_resources = ARRAY_SIZE(ep93xx_a_gpio_resources),
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.resource = ep93xx_a_gpio_resources,
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};
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/* port B */
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static struct resource ep93xx_b_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"),
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB),
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};
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static struct platform_device ep93xx_b_gpio = {
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.name = "gpio-ep93xx",
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.id = 1,
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.num_resources = ARRAY_SIZE(ep93xx_b_gpio_resources),
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.resource = ep93xx_b_gpio_resources,
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};
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/* port C */
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static struct resource ep93xx_c_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"),
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};
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static struct platform_device ep93xx_c_gpio = {
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.name = "gpio-ep93xx",
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.id = 2,
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.num_resources = ARRAY_SIZE(ep93xx_c_gpio_resources),
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.resource = ep93xx_c_gpio_resources,
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};
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/* port D */
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static struct resource ep93xx_d_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"),
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};
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static struct platform_device ep93xx_d_gpio = {
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.name = "gpio-ep93xx",
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.id = 3,
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.num_resources = ARRAY_SIZE(ep93xx_d_gpio_resources),
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.resource = ep93xx_d_gpio_resources,
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};
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/* port E */
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static struct resource ep93xx_e_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"),
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};
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static struct platform_device ep93xx_e_gpio = {
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.name = "gpio-ep93xx",
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.id = 4,
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.num_resources = ARRAY_SIZE(ep93xx_e_gpio_resources),
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.resource = ep93xx_e_gpio_resources,
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};
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/* port F */
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static struct resource ep93xx_f_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"),
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX),
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX),
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX),
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@ -152,11 +224,34 @@ static struct resource ep93xx_gpio_resource[] = {
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DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX),
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};
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static struct platform_device ep93xx_gpio_device = {
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.name = "gpio-ep93xx",
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.id = -1,
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.num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
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.resource = ep93xx_gpio_resource,
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static struct platform_device ep93xx_f_gpio = {
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.name = "gpio-ep93xx",
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.id = 5,
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.num_resources = ARRAY_SIZE(ep93xx_f_gpio_resources),
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.resource = ep93xx_f_gpio_resources,
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};
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/* port G */
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static struct resource ep93xx_g_gpio_resources[] = {
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"),
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DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"),
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};
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static struct platform_device ep93xx_g_gpio = {
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.name = "gpio-ep93xx",
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.id = 6,
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.num_resources = ARRAY_SIZE(ep93xx_g_gpio_resources),
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.resource = ep93xx_g_gpio_resources,
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};
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static struct platform_device *ep93xx_gpio_device[] __initdata = {
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&ep93xx_a_gpio,
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&ep93xx_b_gpio,
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&ep93xx_c_gpio,
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&ep93xx_d_gpio,
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&ep93xx_e_gpio,
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&ep93xx_f_gpio,
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&ep93xx_g_gpio,
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};
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/*************************************************************************
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@ -335,9 +430,9 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = {
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.dev_id = "i2c-gpio.0",
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.table = {
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/* Use local offsets on gpiochip/port "G" */
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GPIO_LOOKUP_IDX("G", 1, NULL, 0,
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GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0,
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GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
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GPIO_LOOKUP_IDX("G", 0, NULL, 1,
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GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1,
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GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
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{ }
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},
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@ -441,8 +536,8 @@ static struct gpiod_lookup_table ep93xx_leds_gpio_table = {
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.dev_id = "leds-gpio",
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.table = {
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/* Use local offsets on gpiochip/port "E" */
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GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH),
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{ }
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},
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};
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@ -975,6 +1070,7 @@ static struct device __init *ep93xx_init_soc(void)
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struct device __init *ep93xx_init_devices(void)
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{
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struct device *parent;
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unsigned int i;
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/* Disallow access to MaverickCrunch initially */
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ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
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@ -989,7 +1085,8 @@ struct device __init *ep93xx_init_devices(void)
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parent = ep93xx_init_soc();
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/* Get the GPIO working early, other devices need it */
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platform_device_register(&ep93xx_gpio_device);
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++)
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platform_device_register(ep93xx_gpio_device[i]);
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amba_device_register(&uart1_device, &iomem_resource);
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amba_device_register(&uart2_device, &iomem_resource);
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@ -105,7 +105,7 @@ static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
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static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = {
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.dev_id = "spi0",
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.table = {
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GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW),
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GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW),
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{ },
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},
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};
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@ -268,7 +268,7 @@ static struct spi_board_info bk3_spi_board_info[] __initdata = {
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static struct gpiod_lookup_table bk3_spi_cs_gpio_table = {
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.dev_id = "spi0",
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.table = {
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GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW),
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GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW),
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{ },
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},
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};
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@ -318,7 +318,7 @@ static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table = {
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.dev_id = "spi0",
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.table = {
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/* DIO_17 */
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GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW),
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GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW),
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{ },
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},
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};
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@ -206,9 +206,9 @@ static struct gpiod_lookup_table vision_spi_mmc_gpio_table = {
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.dev_id = "mmc_spi.2", /* "mmc_spi @ CS2 */
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.table = {
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/* Card detect */
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GPIO_LOOKUP_IDX("B", 7, NULL, 0, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW),
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/* Write protect */
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GPIO_LOOKUP_IDX("F", 0, NULL, 1, GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH),
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{ },
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},
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};
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@ -253,9 +253,9 @@ static struct gpiod_lookup_table vision_spi_cs4271_gpio_table = {
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static struct gpiod_lookup_table vision_spi_cs_gpio_table = {
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.dev_id = "spi0",
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.table = {
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GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("G", 2, "cs", 2, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW),
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GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW),
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{ },
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},
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};
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@ -18,30 +18,10 @@
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#include <linux/gpio/driver.h>
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#include <linux/bitops.h>
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#include <linux/seq_file.h>
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#define EP93XX_GPIO_F_INT_STATUS 0x5c
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#define EP93XX_GPIO_A_INT_STATUS 0xa0
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#define EP93XX_GPIO_B_INT_STATUS 0xbc
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/* Maximum value for gpio line identifiers */
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#define EP93XX_GPIO_LINE_MAX 63
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/* Number of GPIO chips in EP93XX */
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#define EP93XX_GPIO_CHIP_NUM 8
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/* Maximum value for irq capable line identifiers */
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#define EP93XX_GPIO_LINE_MAX_IRQ 23
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#define EP93XX_GPIO_A_IRQ_BASE 64
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#define EP93XX_GPIO_B_IRQ_BASE 72
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/*
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* Static mapping of GPIO bank F IRQS:
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* F0..F7 (16..24) to irq 80..87.
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*/
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#define EP93XX_GPIO_F_IRQ_BASE 80
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#include <linux/interrupt.h>
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struct ep93xx_gpio_irq_chip {
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u8 irq_offset;
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void __iomem *base;
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u8 int_unmasked;
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u8 int_enabled;
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u8 int_type1;
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@ -50,15 +30,11 @@ struct ep93xx_gpio_irq_chip {
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};
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struct ep93xx_gpio_chip {
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void __iomem *base;
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struct gpio_chip gc;
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struct ep93xx_gpio_irq_chip *eic;
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};
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struct ep93xx_gpio {
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void __iomem *base;
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struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
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};
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#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
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static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
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@ -79,25 +55,23 @@ static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc
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#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
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#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
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static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
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struct ep93xx_gpio_irq_chip *eic)
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static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)
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{
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writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);
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writeb_relaxed(eic->int_type2,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
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eic->base + EP93XX_INT_TYPE2_OFFSET);
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writeb_relaxed(eic->int_type1,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
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eic->base + EP93XX_INT_TYPE1_OFFSET);
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writeb_relaxed(eic->int_unmasked & eic->int_enabled,
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epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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eic->base + EP93XX_INT_EN_OFFSET);
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}
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static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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{
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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int port_mask = BIT(offset);
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@ -106,53 +80,43 @@ static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
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else
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eic->int_debounce &= ~port_mask;
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writeb(eic->int_debounce,
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epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
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writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);
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}
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static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
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static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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unsigned long stat;
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int offset;
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chained_irq_enter(irqchip, desc);
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/*
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* Dispatch the IRQs to the irqdomain of each A and B
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* gpiochip irqdomains depending on what has fired.
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* The tricky part is that the IRQ line is shared
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* between bank A and B and each has their own gpiochip.
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*/
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stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
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stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
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offset);
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generic_handle_domain_irq(gc->irq.domain, offset);
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stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
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offset);
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return stat;
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}
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chained_irq_exit(irqchip, desc);
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static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id)
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{
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return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id));
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}
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static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continuous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
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*/
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */
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int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct gpio_irq_chip *gic = &gc->irq;
|
||||
unsigned int parent = irq_desc_get_irq(desc);
|
||||
unsigned int i;
|
||||
|
||||
chained_irq_enter(irqchip, desc);
|
||||
generic_handle_irq(gpio_irq);
|
||||
for (i = 0; i < gic->num_parents; i++)
|
||||
if (gic->parents[i] == parent)
|
||||
break;
|
||||
|
||||
if (i < gic->num_parents)
|
||||
generic_handle_domain_irq(gc->irq.domain, i);
|
||||
|
||||
chained_irq_exit(irqchip, desc);
|
||||
}
|
||||
|
||||
@ -160,31 +124,29 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
|
||||
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
||||
int port_mask = BIT(d->irq & 7);
|
||||
int port_mask = BIT(irqd_to_hwirq(d));
|
||||
|
||||
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
|
||||
eic->int_type2 ^= port_mask; /* switch edge direction */
|
||||
ep93xx_gpio_update_int_params(epg, eic);
|
||||
ep93xx_gpio_update_int_params(eic);
|
||||
}
|
||||
|
||||
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
|
||||
writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
|
||||
}
|
||||
|
||||
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
|
||||
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
||||
int port_mask = BIT(d->irq & 7);
|
||||
int port_mask = BIT(irqd_to_hwirq(d));
|
||||
|
||||
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
|
||||
eic->int_type2 ^= port_mask; /* switch edge direction */
|
||||
|
||||
eic->int_unmasked &= ~port_mask;
|
||||
ep93xx_gpio_update_int_params(epg, eic);
|
||||
ep93xx_gpio_update_int_params(eic);
|
||||
|
||||
writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
|
||||
writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
|
||||
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
|
||||
}
|
||||
|
||||
@ -192,10 +154,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
|
||||
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
||||
|
||||
eic->int_unmasked &= ~BIT(d->irq & 7);
|
||||
ep93xx_gpio_update_int_params(epg, eic);
|
||||
eic->int_unmasked &= ~BIT(irqd_to_hwirq(d));
|
||||
ep93xx_gpio_update_int_params(eic);
|
||||
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
|
||||
}
|
||||
|
||||
@ -203,11 +164,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
|
||||
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
||||
|
||||
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
|
||||
eic->int_unmasked |= BIT(d->irq & 7);
|
||||
ep93xx_gpio_update_int_params(epg, eic);
|
||||
eic->int_unmasked |= BIT(irqd_to_hwirq(d));
|
||||
ep93xx_gpio_update_int_params(eic);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -219,8 +179,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
|
||||
struct ep93xx_gpio *epg = gpiochip_get_data(gc);
|
||||
int offset = d->irq & 7;
|
||||
irq_hw_number_t offset = irqd_to_hwirq(d);
|
||||
int port_mask = BIT(offset);
|
||||
irq_flow_handler_t handler;
|
||||
|
||||
@ -264,51 +223,11 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
|
||||
eic->int_enabled |= port_mask;
|
||||
|
||||
ep93xx_gpio_update_int_params(epg, eic);
|
||||
ep93xx_gpio_update_int_params(eic);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* gpiolib interface for EP93xx on-chip GPIOs
|
||||
*************************************************************************/
|
||||
struct ep93xx_gpio_bank {
|
||||
const char *label;
|
||||
int data;
|
||||
int dir;
|
||||
int irq;
|
||||
int base;
|
||||
bool has_irq;
|
||||
bool has_hierarchical_irq;
|
||||
unsigned int irq_base;
|
||||
};
|
||||
|
||||
#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
|
||||
{ \
|
||||
.label = _label, \
|
||||
.data = _data, \
|
||||
.dir = _dir, \
|
||||
.irq = _irq, \
|
||||
.base = _base, \
|
||||
.has_irq = _has_irq, \
|
||||
.has_hierarchical_irq = _has_hier, \
|
||||
.irq_base = _irq_base, \
|
||||
}
|
||||
|
||||
static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
|
||||
/* Bank A has 8 IRQs */
|
||||
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
|
||||
/* Bank B has 8 IRQs */
|
||||
EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
|
||||
EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
|
||||
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
|
||||
EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
|
||||
/* Bank F has 8 IRQs */
|
||||
EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
|
||||
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
|
||||
EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
|
||||
};
|
||||
|
||||
static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
|
||||
unsigned long config)
|
||||
{
|
||||
@ -342,110 +261,102 @@ static const struct irq_chip gpio_eic_irq_chip = {
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
|
||||
struct platform_device *pdev,
|
||||
struct ep93xx_gpio *epg,
|
||||
struct ep93xx_gpio_bank *bank)
|
||||
static int ep93xx_setup_irqs(struct platform_device *pdev,
|
||||
struct ep93xx_gpio_chip *egc)
|
||||
{
|
||||
void __iomem *data = epg->base + bank->data;
|
||||
void __iomem *dir = epg->base + bank->dir;
|
||||
struct gpio_chip *gc = &egc->gc;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct gpio_irq_chip *girq;
|
||||
int err;
|
||||
struct gpio_irq_chip *girq = &gc->irq;
|
||||
int ret, irq, i;
|
||||
void __iomem *intr;
|
||||
|
||||
err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
|
||||
if (err)
|
||||
return err;
|
||||
intr = devm_platform_ioremap_resource_byname(pdev, "intr");
|
||||
if (IS_ERR(intr))
|
||||
return PTR_ERR(intr);
|
||||
|
||||
gc->label = bank->label;
|
||||
gc->base = bank->base;
|
||||
gc->set_config = ep93xx_gpio_set_config;
|
||||
egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);
|
||||
if (!egc->eic)
|
||||
return -ENOMEM;
|
||||
|
||||
girq = &gc->irq;
|
||||
if (bank->has_irq || bank->has_hierarchical_irq) {
|
||||
gc->set_config = ep93xx_gpio_set_config;
|
||||
egc->eic = devm_kcalloc(dev, 1,
|
||||
sizeof(*egc->eic),
|
||||
GFP_KERNEL);
|
||||
if (!egc->eic)
|
||||
return -ENOMEM;
|
||||
egc->eic->irq_offset = bank->irq;
|
||||
gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
|
||||
}
|
||||
egc->eic->base = intr;
|
||||
gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
|
||||
girq->num_parents = platform_irq_count(pdev);
|
||||
if (girq->num_parents == 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (bank->has_irq) {
|
||||
int ab_parent_irq = platform_get_irq(pdev, 0);
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
|
||||
girq->parent_handler = ep93xx_gpio_ab_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_level_irq;
|
||||
girq->parents[0] = ab_parent_irq;
|
||||
girq->first = bank->irq_base;
|
||||
}
|
||||
if (girq->num_parents == 1) { /* A/B irqchips */
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
/* Only bank F has especially funky IRQ handling */
|
||||
if (bank->has_hierarchical_irq) {
|
||||
int gpio_irq;
|
||||
int i;
|
||||
ret = devm_request_irq(dev, irq, ep93xx_ab_irq_handler,
|
||||
IRQF_SHARED, gc->label, gc);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq);
|
||||
|
||||
/*
|
||||
* FIXME: convert this to use hierarchical IRQ support!
|
||||
* this requires fixing the root irqchip to be hierarchical.
|
||||
*/
|
||||
girq->parents[0] = irq;
|
||||
} else { /* F irqchip */
|
||||
girq->parent_handler = ep93xx_gpio_f_irq_handler;
|
||||
girq->num_parents = 8;
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents),
|
||||
GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
/* Pick resources 1..8 for these IRQs */
|
||||
|
||||
for (i = 0; i < girq->num_parents; i++) {
|
||||
girq->parents[i] = platform_get_irq(pdev, i + 1);
|
||||
gpio_irq = bank->irq_base + i;
|
||||
irq_set_chip_data(gpio_irq, &epg->gc[5]);
|
||||
irq_set_chip_and_handler(gpio_irq,
|
||||
girq->chip,
|
||||
handle_level_irq);
|
||||
irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
continue;
|
||||
|
||||
girq->parents[i] = irq;
|
||||
}
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_level_irq;
|
||||
girq->first = bank->irq_base;
|
||||
|
||||
girq->map = girq->parents;
|
||||
}
|
||||
|
||||
return devm_gpiochip_add_data(dev, gc, epg);
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
/* TODO: replace with handle_bad_irq() once we are fully hierarchical */
|
||||
girq->handler = handle_simple_irq;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ep93xx_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ep93xx_gpio *epg;
|
||||
int i;
|
||||
struct ep93xx_gpio_chip *egc;
|
||||
struct gpio_chip *gc;
|
||||
void __iomem *data;
|
||||
void __iomem *dir;
|
||||
int ret;
|
||||
|
||||
epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
|
||||
if (!epg)
|
||||
egc = devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL);
|
||||
if (!egc)
|
||||
return -ENOMEM;
|
||||
|
||||
epg->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(epg->base))
|
||||
return PTR_ERR(epg->base);
|
||||
data = devm_platform_ioremap_resource_byname(pdev, "data");
|
||||
if (IS_ERR(data))
|
||||
return PTR_ERR(data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
|
||||
struct ep93xx_gpio_chip *gc = &epg->gc[i];
|
||||
struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
|
||||
dir = devm_platform_ioremap_resource_byname(pdev, "dir");
|
||||
if (IS_ERR(dir))
|
||||
return PTR_ERR(dir);
|
||||
|
||||
if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
|
||||
dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
|
||||
bank->label);
|
||||
gc = &egc->gc;
|
||||
ret = bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n");
|
||||
|
||||
gc->label = dev_name(&pdev->dev);
|
||||
if (platform_irq_count(pdev) > 0) {
|
||||
dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev));
|
||||
ret = ep93xx_setup_irqs(pdev, egc);
|
||||
if (ret)
|
||||
dev_err_probe(&pdev->dev, ret, "setup irqs failed");
|
||||
}
|
||||
|
||||
return 0;
|
||||
return devm_gpiochip_add_data(&pdev->dev, gc, egc);
|
||||
}
|
||||
|
||||
static struct platform_driver ep93xx_gpio_driver = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user