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rtl8xxxu: Fix 8188RU support
The 8188RU does not like PAPE to be enabled, while all the other gen1 parts seem to require it. This makes the RTL8188RU able to associate for me. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -3145,6 +3145,7 @@ static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
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sprintf(priv->chip_name, "8188RU");
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priv->rtl_chip = RTL8188R;
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priv->hi_pa = 1;
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priv->no_pape = 1;
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priv->power_base = &rtl8188r_power_base;
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}
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@ -5555,9 +5556,12 @@ static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
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rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
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rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
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val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
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val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
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rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
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if (!priv->no_pape) {
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val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
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val32 |= (FPGA0_RF_PAPE |
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(FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
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rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
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}
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val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
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val32 &= ~BIT(10);
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@ -7804,11 +7808,14 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
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val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
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FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
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((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
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FPGA0_RF_BD_CTRL_SHIFT);
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FPGA0_RF_ANTSWB |
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((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
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if (!priv->no_pape) {
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val32 |= (FPGA0_RF_PAPE |
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(FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
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}
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rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
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/* 0x860[6:5]= 00 - why? - this sets antenna B */
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if (priv->rtl_chip != RTL8192E)
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rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
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@ -1287,6 +1287,7 @@ struct rtl8xxxu_priv {
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u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
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enum rtl8xxxu_rtl_chip rtl_chip;
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u8 pi_enabled:1;
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u8 no_pape:1;
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u8 int_buf[USB_INTR_CONTENT_LENGTH];
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};
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