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arm64: dts: qcom: sdm845: Add USB-related nodes
This adds nodes for USB and related PHYs. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> [dianders: reworked quite a bit] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Manu Gautam
Andy Gross
parent
ead5eea3e3
commit
ca4db2b538
@ -8,6 +8,7 @@
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy-qcom-qusb2.h>
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#include <dt-bindings/reset/qcom,sdm845-aoss.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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@ -250,6 +251,23 @@
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#power-domain-cells = <1>;
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};
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qfprom@784000 {
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compatible = "qcom,qfprom";
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reg = <0x784000 0x8ff>;
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#address-cells = <1>;
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#size-cells = <1>;
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qusb2p_hstx_trim: hstx-trim-primary@1eb {
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reg = <0x1eb 0x1>;
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bits = <1 4>;
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};
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qusb2s_hstx_trim: hstx-trim-secondary@1eb {
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reg = <0x1eb 0x2>;
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bits = <6 4>;
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};
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};
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qupv3_id_0: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x6000>;
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@ -963,6 +981,184 @@
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};
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};
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usb_1_hsphy: phy@88e2000 {
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compatible = "qcom,sdm845-qusb2-phy";
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reg = <0x88e2000 0x400>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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usb_2_hsphy: phy@88e3000 {
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compatible = "qcom,sdm845-qusb2-phy";
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reg = <0x88e3000 0x400>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "cfg_ahb", "ref";
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resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
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nvmem-cells = <&qusb2s_hstx_trim>;
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};
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usb_1_qmpphy: phy@88e9000 {
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compatible = "qcom,sdm845-qmp-usb3-phy";
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reg = <0x88e9000 0x18c>,
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<0x88e8000 0x10>;
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reg-names = "reg-base", "dp_com";
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "com_aux";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "phy", "common";
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usb_1_ssphy: lane@88e9200 {
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reg = <0x88e9200 0x128>,
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<0x88e9400 0x200>,
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<0x88e9c00 0x218>,
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<0x88e9a00 0x100>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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};
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usb_2_qmpphy: phy@88eb000 {
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compatible = "qcom,sdm845-qmp-usb3-uni-phy";
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reg = <0x88eb000 0x18c>;
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_SEC_CLKREF_CLK>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "com_aux";
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resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
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<&gcc GCC_USB3_PHY_SEC_BCR>;
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reset-names = "phy", "common";
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usb_2_ssphy: lane@88eb200 {
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reg = <0x88eb200 0x128>,
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<0x88eb400 0x1fc>,
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<0x88eb800 0x218>,
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<0x88e9600 0x70>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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};
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};
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usb_1: usb@a6f8800 {
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compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
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reg = <0xa6f8800 0x400>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <150000000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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usb_1_dwc3: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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usb_2: usb@a8f8800 {
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compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
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reg = <0xa8f8800 0x400>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <150000000>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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power-domains = <&gcc USB30_SEC_GDSC>;
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resets = <&gcc GCC_USB30_SEC_BCR>;
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usb_2_dwc3: dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0xa800000 0xcd00>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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tsens0: thermal-sensor@c263000 {
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compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
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reg = <0xc263000 0x1ff>, /* TM */
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