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media: ti-vpe: cal: Move function to avoid forward declaration

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Move the csi2_phy_config() function to avoid its forward declaration. No
functional change is included.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart 2020-07-06 20:35:44 +02:00 committed by Mauro Carvalho Chehab
parent 0a19960a6c
commit ca48646850
1 changed files with 48 additions and 50 deletions
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98
drivers/media/platform/ti-vpe/cal.c
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@ -740,7 +740,54 @@ static void csi2_cio_power(struct cal_ctx *ctx, bool enable)
enable ? "up" : "down");
}
static void csi2_phy_config(struct cal_ctx *ctx);
/*
* TCLK values are OK at their reset values
*/
#define TCLK_TERM 0
#define TCLK_MISS 1
#define TCLK_SETTLE 14
static void csi2_phy_config(struct cal_ctx *ctx)
{
unsigned int reg0, reg1;
unsigned int ths_term, ths_settle;
unsigned int csi2_ddrclk_khz;
struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
&ctx->endpoint.bus.mipi_csi2;
u32 num_lanes = mipi_csi2->num_data_lanes;
/* DPHY timing configuration */
/* CSI-2 is DDR and we only count used lanes. */
csi2_ddrclk_khz = ctx->external_rate / 1000
/ (2 * num_lanes) * ctx->fmt->bpp;
ctx_dbg(1, ctx, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
/* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
ths_term = 20 * csi2_ddrclk_khz / 1000000;
ctx_dbg(1, ctx, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
/* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
ctx_dbg(1, ctx, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
reg0 = reg_read(ctx->cc, CAL_CSI2_PHY_REG0);
set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
ctx_dbg(1, ctx, "CSI2_%d_REG0 = 0x%08x\n", ctx->csi2_port, reg0);
reg_write(ctx->cc, CAL_CSI2_PHY_REG0, reg0);
reg1 = reg_read(ctx->cc, CAL_CSI2_PHY_REG1);
set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
set_field(&reg1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x\n", ctx->csi2_port, reg1);
reg_write(ctx->cc, CAL_CSI2_PHY_REG1, reg1);
}
static void csi2_phy_init(struct cal_ctx *ctx)
{
@ -1077,55 +1124,6 @@ static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
reg_write(ctx->dev, CAL_WR_DMA_ADDR(ctx->csi2_port), dmaaddr);
}
/*
* TCLK values are OK at their reset values
*/
#define TCLK_TERM 0
#define TCLK_MISS 1
#define TCLK_SETTLE 14
static void csi2_phy_config(struct cal_ctx *ctx)
{
unsigned int reg0, reg1;
unsigned int ths_term, ths_settle;
unsigned int csi2_ddrclk_khz;
struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
&ctx->endpoint.bus.mipi_csi2;
u32 num_lanes = mipi_csi2->num_data_lanes;
/* DPHY timing configuration */
/* CSI-2 is DDR and we only count used lanes. */
csi2_ddrclk_khz = ctx->external_rate / 1000
/ (2 * num_lanes) * ctx->fmt->bpp;
ctx_dbg(1, ctx, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
/* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
ths_term = 20 * csi2_ddrclk_khz / 1000000;
ctx_dbg(1, ctx, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
/* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
ctx_dbg(1, ctx, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
reg0 = reg_read(ctx->cc, CAL_CSI2_PHY_REG0);
set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
ctx_dbg(1, ctx, "CSI2_%d_REG0 = 0x%08x\n", ctx->csi2_port, reg0);
reg_write(ctx->cc, CAL_CSI2_PHY_REG0, reg0);
reg1 = reg_read(ctx->cc, CAL_CSI2_PHY_REG1);
set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
set_field(&reg1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x\n", ctx->csi2_port, reg1);
reg_write(ctx->cc, CAL_CSI2_PHY_REG1, reg1);
}
static int cal_get_external_info(struct cal_ctx *ctx)
{
struct v4l2_ctrl *ctrl;