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Merge branch 'icc-sm6115' into icc-next

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Add DT bindings and a driver for managing NoC providers on SM6115.

* icc-sm6115
  dt-bindings: interconnect: Add Qualcomm SM6115 NoC
  interconnect: qcom: Add SM6115 interconnect provider driver
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM6115 bwmon instance
  interconnect: qcom: sm6115: Fix up includes

Link: https://lore.kernel.org/r/20231125-topic-6115icc-v3-2-bd8907b8cfd7@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2023-12-15 00:42:07 +02:00
commit c9de516ef6
6 changed files with 1698 additions and 0 deletions
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1
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
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@ -29,6 +29,7 @@ properties:
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
- qcom,sdm845-cpu-bwmon
- qcom,sm6115-cpu-bwmon
- qcom,sm6350-llcc-bwmon
- qcom,sm8250-cpu-bwmon
- qcom,sm8550-cpu-bwmon

152
Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml Normal file
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@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 Network-On-Chip interconnect
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description:
The Qualcomm SM6115 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-cnoc
- qcom,sm6115-snoc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
$ref: qcom,rpm-common.yaml#
properties:
compatible:
enum:
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
required:
- compatible
unevaluatedProperties: false
required:
- compatible
- reg
allOf:
- $ref: qcom,rpm-common.yaml#
- if:
properties:
compatible:
const: qcom,sm6115-cnoc
then:
properties:
clocks:
items:
- description: USB-NoC AXI clock
clock-names:
items:
- const: usb_axi
- if:
properties:
compatible:
const: qcom,sm6115-snoc
then:
properties:
clocks:
items:
- description: CPU-NoC AXI clock.
- description: UFS-NoC AXI clock.
- description: USB-NoC AXI clock.
- description: IPA clock.
clock-names:
items:
- const: cpu_axi
- const: ufs_axi
- const: usb_axi
- const: ipa
- if:
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
then:
properties:
clocks: false
clock-names: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
snoc: interconnect@1880000 {
compatible = "qcom,sm6115-snoc";
reg = <0x01880000 0x60200>;
clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>;
clock-names = "cpu_axi",
"ufs_axi",
"usb_axi",
"ipa";
#interconnect-cells = <1>;
qup_virt: interconnect-clk {
compatible = "qcom,sm6115-clk-virt";
#interconnect-cells = <1>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,sm6115-mmnrt-virt";
#interconnect-cells = <1>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,sm6115-mmrt-virt";
#interconnect-cells = <1>;
};
};
cnoc: interconnect@1900000 {
compatible = "qcom,sm6115-cnoc";
reg = <0x01900000 0x8200>;
#interconnect-cells = <1>;
};

9
drivers/interconnect/qcom/Kconfig
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@ -191,6 +191,15 @@ config INTERCONNECT_QCOM_SDX75
This is a driver for the Qualcomm Network-on-Chip on sdx75-based
platforms.
config INTERCONNECT_QCOM_SM6115
tristate "Qualcomm SM6115 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on sm6115-based
platforms.
config INTERCONNECT_QCOM_SM6350
tristate "Qualcomm SM6350 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

2
drivers/interconnect/qcom/Makefile
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@ -24,6 +24,7 @@ qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sdx65-objs := sdx65.o
qnoc-sdx75-objs := sdx75.o
qnoc-sm6115-objs := sm6115.o
qnoc-sm6350-objs := sm6350.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
@ -55,6 +56,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o

1423
drivers/interconnect/qcom/sm6115.c Normal file
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111
include/dt-bindings/interconnect/qcom,sm6115.h Normal file
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@ -0,0 +1,111 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
/* BIMC */
#define MASTER_AMPSS_M0 0
#define MASTER_SNOC_BIMC_RT 1
#define MASTER_SNOC_BIMC_NRT 2
#define SNOC_BIMC_MAS 3
#define MASTER_GRAPHICS_3D 4
#define MASTER_TCU_0 5
#define SLAVE_EBI_CH0 6
#define BIMC_SNOC_SLV 7
/* CNOC */
#define SNOC_CNOC_MAS 0
#define MASTER_QDSS_DAP 1
#define SLAVE_AHB2PHY_USB 2
#define SLAVE_APSS_THROTTLE_CFG 3
#define SLAVE_BIMC_CFG 4
#define SLAVE_BOOT_ROM 5
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
#define SLAVE_CAMERA_RT_THROTTLE_CFG 7
#define SLAVE_CAMERA_CFG 8
#define SLAVE_CLK_CTL 9
#define SLAVE_RBCPR_CX_CFG 10
#define SLAVE_RBCPR_MX_CFG 11
#define SLAVE_CRYPTO_0_CFG 12
#define SLAVE_DCC_CFG 13
#define SLAVE_DDR_PHY_CFG 14
#define SLAVE_DDR_SS_CFG 15
#define SLAVE_DISPLAY_CFG 16
#define SLAVE_DISPLAY_THROTTLE_CFG 17
#define SLAVE_GPU_CFG 18
#define SLAVE_GPU_THROTTLE_CFG 19
#define SLAVE_HWKM_CORE 20
#define SLAVE_IMEM_CFG 21
#define SLAVE_IPA_CFG 22
#define SLAVE_LPASS 23
#define SLAVE_MAPSS 24
#define SLAVE_MDSP_MPU_CFG 25
#define SLAVE_MESSAGE_RAM 26
#define SLAVE_CNOC_MSS 27
#define SLAVE_PDM 28
#define SLAVE_PIMEM_CFG 29
#define SLAVE_PKA_CORE 30
#define SLAVE_PMIC_ARB 31
#define SLAVE_QDSS_CFG 32
#define SLAVE_QM_CFG 33
#define SLAVE_QM_MPU_CFG 34
#define SLAVE_QPIC 35
#define SLAVE_QUP_0 36
#define SLAVE_RPM 37
#define SLAVE_SDCC_1 38
#define SLAVE_SDCC_2 39
#define SLAVE_SECURITY 40
#define SLAVE_SNOC_CFG 41
#define SLAVE_TCSR 42
#define SLAVE_TLMM 43
#define SLAVE_USB3 44
#define SLAVE_VENUS_CFG 45
#define SLAVE_VENUS_THROTTLE_CFG 46
#define SLAVE_VSENSE_CTRL_CFG 47
#define SLAVE_SERVICE_CNOC 48
/* SNOC */
#define MASTER_CRYPTO_CORE0 0
#define MASTER_SNOC_CFG 1
#define MASTER_TIC 2
#define MASTER_ANOC_SNOC 3
#define BIMC_SNOC_MAS 4
#define MASTER_PIMEM 5
#define MASTER_QDSS_BAM 6
#define MASTER_QPIC 7
#define MASTER_QUP_0 8
#define MASTER_IPA 9
#define MASTER_QDSS_ETR 10
#define MASTER_SDCC_1 11
#define MASTER_SDCC_2 12
#define MASTER_USB3 13
#define SLAVE_APPSS 14
#define SNOC_CNOC_SLV 15
#define SLAVE_OCIMEM 16
#define SLAVE_PIMEM 17
#define SNOC_BIMC_SLV 18
#define SLAVE_SERVICE_SNOC 19
#define SLAVE_QDSS_STM 20
#define SLAVE_TCU 21
#define SLAVE_ANOC_SNOC 22
/* CLK Virtual */
#define MASTER_QUP_CORE_0 0
#define SLAVE_QUP_CORE_0 1
/* MMRT Virtual */
#define MASTER_CAMNOC_HF 0
#define MASTER_MDP_PORT0 1
#define SLAVE_SNOC_BIMC_RT 2
/* MMNRT Virtual */
#define MASTER_CAMNOC_SF 0
#define MASTER_VIDEO_P0 1
#define MASTER_VIDEO_PROC 2
#define SLAVE_SNOC_BIMC_NRT 3
#endif