cpufreq: imx-cpufreq-dt: Correct i.MX8MP's market segment fuse location

i.MX8MP's market segment fuse field is bit[6:5], correct it.

Fixes: 83fe39ad0a ("cpufreq: imx-cpufreq-dt: Add i.MX8MP support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Anson Huang 2020-03-10 13:48:16 +08:00 committed by Viresh Kumar
parent 4bd8459b6c
commit c98330446c

View File

@ -19,6 +19,8 @@
#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5
#define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5)
/* cpufreq-dt device registered by imx-cpufreq-dt */
static struct platform_device *cpufreq_dt_pdev;
@ -45,7 +47,13 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
else
speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
>> OCOTP_CFG3_SPEED_GRADE_SHIFT;
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
if (of_machine_is_compatible("fsl,imx8mp"))
mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)
>> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;
else
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)
>> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
/*
* Early samples without fuses written report "0 0" which may NOT