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PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge

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Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but
comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be
hardwired to zero but mvebu hw allows to change it.

Link: https://lore.kernel.org/r/20220104153529.31647-11-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Pali Rohár 2022-01-04 16:35:28 +01:00 committed by Lorenzo Pieralisi
parent d76a6ed096
commit c94ea32c0d
1 changed files with 3 additions and 4 deletions
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7
drivers/pci/controller/pci-mvebu.c
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@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
case PCI_EXP_LNKCTL:
/*
* If we don't support CLKREQ, we must ensure that the
* CLKREQ enable bit always reads zero. Since we haven't
* had this capability, and it's dependent on board wiring,
* disable it for the time being.
* PCIe requires that the Enable Clock Power Management bit
* is hard-wired to zero for downstream ports but HW allows
* to change it.
*/
new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;