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edac/85xx: Add PCIe error interrupt edac support
Add pcie error interrupt edac support for mpc85xx, p3041, p4080, and p5020. The mpc85xx uses the legacy interrupt report mechanism - the error interrupts are reported directly to mpic. While the p3041/ p4080/p5020 attaches the most of error interrupts to interrupt zero. And report error interrupts to mpic via interrupt 0. This patch can handle both of them. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Link: http://lkml.kernel.org/r/1384712714-8826-3-git-send-email-morbidrsa@gmail.com Cc: Doug Thompson <dougthompson@xmission.com> Cc: Dave Jiang <dave.jiang@gmail.com> Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de> Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Chunhe Lan
Borislav Petkov
parent
6ce4eac1f6
commit
c92132f598
@ -1,6 +1,8 @@
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/*
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* Freescale MPC85xx Memory Controller kenel module
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*
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* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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@ -196,6 +198,42 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
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edac_pci_handle_npe(pci, pci->ctl_name);
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}
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static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
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{
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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pr_err("PCIe error(s) detected\n");
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pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
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pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR));
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pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
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pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
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pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
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pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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}
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static int mpc85xx_pcie_find_capability(struct device_node *np)
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{
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struct pci_controller *hose;
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if (!np)
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return -EINVAL;
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hose = pci_find_hose_for_OF_device(np);
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return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
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}
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static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
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{
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struct edac_pci_ctl_info *pci = dev_id;
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@ -207,7 +245,10 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
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if (!err_detect)
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return IRQ_NONE;
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mpc85xx_pci_check(pci);
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if (pdata->is_pcie)
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mpc85xx_pcie_check(pci);
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else
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mpc85xx_pci_check(pci);
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return IRQ_HANDLED;
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}
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@ -239,14 +280,22 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
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pdata = pci->pvt_info;
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pdata->name = "mpc85xx_pci_err";
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pdata->irq = NO_IRQ;
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if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0)
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pdata->is_pcie = true;
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dev_set_drvdata(&op->dev, pci);
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pci->dev = &op->dev;
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pci->mod_name = EDAC_MOD_STR;
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pci->ctl_name = pdata->name;
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pci->dev_name = dev_name(&op->dev);
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if (edac_op_state == EDAC_OPSTATE_POLL)
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pci->edac_check = mpc85xx_pci_check;
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if (edac_op_state == EDAC_OPSTATE_POLL) {
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if (pdata->is_pcie)
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pci->edac_check = mpc85xx_pcie_check;
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else
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pci->edac_check = mpc85xx_pci_check;
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}
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pdata->edac_idx = edac_pci_idx++;
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@ -275,16 +324,26 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
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goto err;
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}
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
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if (pdata->is_pcie) {
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
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orig_pci_err_en =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
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} else {
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
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/* PCI master abort is expected during config cycles */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
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/* PCI master abort is expected during config cycles */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
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orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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orig_pci_err_en =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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/* disable master abort reporting */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
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/* disable master abort reporting */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
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}
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
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@ -297,7 +356,8 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
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if (edac_op_state == EDAC_OPSTATE_INT) {
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pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
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res = devm_request_irq(&op->dev, pdata->irq,
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mpc85xx_pci_isr, IRQF_DISABLED,
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mpc85xx_pci_isr,
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IRQF_DISABLED | IRQF_SHARED,
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"[EDAC] PCI err", pci);
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if (res < 0) {
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printk(KERN_ERR
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@ -312,6 +372,22 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
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pdata->irq);
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}
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if (pdata->is_pcie) {
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/*
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* Enable all PCIe error interrupt & error detect except invalid
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* PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
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* enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
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* detection enable bit. Because PCIe bus code to initialize and
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* configure these PCIe devices on booting will use some invalid
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* PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
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* notice information. So disable this detect to fix ugly print.
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*/
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
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& ~PEX_ERR_ICCAIE_EN_BIT);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
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| PEX_ERR_ICCAD_DISR_BIT);
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}
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devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
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edac_dbg(3, "success\n");
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printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
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@ -134,13 +134,19 @@
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#define MPC85XX_PCI_ERR_DR 0x0000
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#define MPC85XX_PCI_ERR_CAP_DR 0x0004
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#define MPC85XX_PCI_ERR_EN 0x0008
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#define PEX_ERR_ICCAIE_EN_BIT 0x00020000
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#define MPC85XX_PCI_ERR_ATTRIB 0x000c
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#define MPC85XX_PCI_ERR_ADDR 0x0010
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#define PEX_ERR_ICCAD_DISR_BIT 0x00020000
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#define MPC85XX_PCI_ERR_EXT_ADDR 0x0014
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#define MPC85XX_PCI_ERR_DL 0x0018
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#define MPC85XX_PCI_ERR_DH 0x001c
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#define MPC85XX_PCI_GAS_TIMR 0x0020
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#define MPC85XX_PCI_PCIX_TIMR 0x0024
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#define MPC85XX_PCIE_ERR_CAP_R0 0x0028
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#define MPC85XX_PCIE_ERR_CAP_R1 0x002c
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#define MPC85XX_PCIE_ERR_CAP_R2 0x0030
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#define MPC85XX_PCIE_ERR_CAP_R3 0x0034
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struct mpc85xx_mc_pdata {
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char *name;
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@ -158,6 +164,7 @@ struct mpc85xx_l2_pdata {
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struct mpc85xx_pci_pdata {
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char *name;
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bool is_pcie;
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int edac_idx;
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void __iomem *pci_vbase;
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int irq;
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