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drm/amd/display: Expose new CRC window property
[Why] Instead of calculating CRC on whole frame, add flexibility to calculate CRC on specific frame region. [How] Add few crc window coordinate properties. By default, CRC is calculated on whole frame unless user space specifies the CRC calculation window. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c88840f342
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c920888c60
@ -943,6 +943,41 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
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}
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#endif
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#ifdef CONFIG_DEBUG_FS
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static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
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{
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dm->crc_win_x_start_property =
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drm_property_create_range(adev_to_drm(dm->adev),
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DRM_MODE_PROP_ATOMIC,
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"AMD_CRC_WIN_X_START", 0, U16_MAX);
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if (!dm->crc_win_x_start_property)
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return -ENOMEM;
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dm->crc_win_y_start_property =
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drm_property_create_range(adev_to_drm(dm->adev),
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DRM_MODE_PROP_ATOMIC,
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"AMD_CRC_WIN_Y_START", 0, U16_MAX);
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if (!dm->crc_win_y_start_property)
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return -ENOMEM;
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dm->crc_win_x_end_property =
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drm_property_create_range(adev_to_drm(dm->adev),
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DRM_MODE_PROP_ATOMIC,
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"AMD_CRC_WIN_X_END", 0, U16_MAX);
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if (!dm->crc_win_x_end_property)
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return -ENOMEM;
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dm->crc_win_y_end_property =
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drm_property_create_range(adev_to_drm(dm->adev),
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DRM_MODE_PROP_ATOMIC,
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"AMD_CRC_WIN_Y_END", 0, U16_MAX);
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if (!dm->crc_win_y_end_property)
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return -ENOMEM;
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return 0;
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}
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#endif
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static int amdgpu_dm_init(struct amdgpu_device *adev)
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{
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struct dc_init_data init_data;
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@ -1084,6 +1119,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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dc_init_callbacks(adev->dm.dc, &init_params);
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}
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#endif
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#ifdef CONFIG_DEBUG_FS
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if (create_crtc_crc_properties(&adev->dm))
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DRM_ERROR("amdgpu: failed to create crc property.\n");
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#endif
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if (amdgpu_dm_initialize_drm_device(adev)) {
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DRM_ERROR(
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@ -5250,12 +5289,64 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
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state->crc_src = cur->crc_src;
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state->cm_has_degamma = cur->cm_has_degamma;
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state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
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#ifdef CONFIG_DEBUG_FS
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state->crc_window = cur->crc_window;
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#endif
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/* TODO Duplicate dc_stream after objects are stream object is flattened */
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return &state->base;
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}
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#ifdef CONFIG_DEBUG_FS
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int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state,
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struct drm_property *property,
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uint64_t val)
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{
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = drm_to_adev(dev);
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struct dm_crtc_state *dm_new_state =
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to_dm_crtc_state(crtc_state);
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if (property == adev->dm.crc_win_x_start_property)
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dm_new_state->crc_window.x_start = val;
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else if (property == adev->dm.crc_win_y_start_property)
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dm_new_state->crc_window.y_start = val;
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else if (property == adev->dm.crc_win_x_end_property)
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dm_new_state->crc_window.x_end = val;
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else if (property == adev->dm.crc_win_y_end_property)
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dm_new_state->crc_window.y_end = val;
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else
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return -EINVAL;
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return 0;
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}
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int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
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const struct drm_crtc_state *state,
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struct drm_property *property,
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uint64_t *val)
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{
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = drm_to_adev(dev);
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struct dm_crtc_state *dm_state =
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to_dm_crtc_state(state);
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if (property == adev->dm.crc_win_x_start_property)
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*val = dm_state->crc_window.x_start;
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else if (property == adev->dm.crc_win_y_start_property)
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*val = dm_state->crc_window.y_start;
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else if (property == adev->dm.crc_win_x_end_property)
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*val = dm_state->crc_window.x_end;
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else if (property == adev->dm.crc_win_y_end_property)
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*val = dm_state->crc_window.y_end;
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else
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return -EINVAL;
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return 0;
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}
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#endif
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static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
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{
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enum dc_irq_source irq_source;
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@ -5322,6 +5413,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
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.enable_vblank = dm_enable_vblank,
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.disable_vblank = dm_disable_vblank,
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.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
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#ifdef CONFIG_DEBUG_FS
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.atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
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.atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
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#endif
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};
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static enum drm_connector_status
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@ -6519,6 +6614,25 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
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struct amdgpu_crtc *acrtc)
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{
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drm_object_attach_property(&acrtc->base.base,
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dm->crc_win_x_start_property,
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0);
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drm_object_attach_property(&acrtc->base.base,
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dm->crc_win_y_start_property,
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0);
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drm_object_attach_property(&acrtc->base.base,
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dm->crc_win_x_end_property,
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0);
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drm_object_attach_property(&acrtc->base.base,
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dm->crc_win_y_end_property,
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0);
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}
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#endif
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static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
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struct drm_plane *plane,
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uint32_t crtc_index)
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@ -6566,7 +6680,9 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
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drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
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true, MAX_COLOR_LUT_ENTRIES);
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drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
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#ifdef CONFIG_DEBUG_FS
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attach_crtc_crc_properties(dm, acrtc);
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#endif
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return 0;
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fail:
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@ -8190,6 +8306,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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*/
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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bool configure_crc = false;
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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@ -8199,21 +8316,30 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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dc_stream_retain(dm_new_crtc_state->stream);
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acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
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manage_dm_interrupts(adev, acrtc, true);
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}
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#ifdef CONFIG_DEBUG_FS
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if (new_crtc_state->active &&
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amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
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/**
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* Frontend may have changed so reapply the CRC capture
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* settings for the stream.
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*/
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
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amdgpu_dm_crtc_configure_crc_source(
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crtc, dm_new_crtc_state,
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dm_new_crtc_state->crc_src);
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if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
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if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))
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configure_crc = true;
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} else {
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if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
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configure_crc = true;
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}
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#endif
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if (configure_crc)
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amdgpu_dm_crtc_configure_crc_source(
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crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);
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}
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#endif
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}
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for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
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@ -336,6 +336,13 @@ struct amdgpu_display_manager {
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*/
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const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
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#ifdef CONFIG_DEBUG_FS
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/* set the crc calculation window*/
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struct drm_property *crc_win_x_start_property;
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struct drm_property *crc_win_y_start_property;
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struct drm_property *crc_win_x_end_property;
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struct drm_property *crc_win_y_end_property;
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#endif
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/**
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* @mst_encoders:
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*
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@ -422,6 +429,15 @@ struct dm_plane_state {
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struct dc_plane_state *dc_state;
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};
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#ifdef CONFIG_DEBUG_FS
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struct crc_rec {
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uint16_t x_start;
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uint16_t y_start;
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uint16_t x_end;
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uint16_t y_end;
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};
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#endif
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struct dm_crtc_state {
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struct drm_crtc_state base;
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struct dc_stream_state *stream;
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@ -444,6 +460,9 @@ struct dm_crtc_state {
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struct dc_info_packet vrr_infopacket;
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int abm_level;
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#ifdef CONFIG_DEBUG_FS
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struct crc_rec crc_window;
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#endif
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};
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#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
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@ -81,6 +81,33 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
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return pipe_crc_sources;
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}
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bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
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{
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bool ret = true;
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if ((dm_crtc_state->crc_window.x_start != 0) ||
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(dm_crtc_state->crc_window.y_start != 0) ||
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(dm_crtc_state->crc_window.x_end != 0) ||
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(dm_crtc_state->crc_window.y_end != 0))
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ret = false;
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return ret;
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}
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bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
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struct dm_crtc_state *dm_old_crtc_state)
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{
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bool ret = false;
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if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) ||
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(dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) ||
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(dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) ||
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(dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
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ret = true;
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return ret;
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}
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int
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amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
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size_t *values_cnt)
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@ -105,6 +132,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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struct dc_stream_state *stream_state = dm_crtc_state->stream;
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bool enable = amdgpu_dm_is_valid_crc_source(source);
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int ret = 0;
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struct crc_params *crc_window = NULL, tmp_window;
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/* Configuration will be deferred to stream enable. */
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if (!stream_state)
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@ -114,8 +142,21 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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/* Enable CRTC CRC generation if necessary. */
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if (dm_is_crc_source_crtc(source)) {
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if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
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crc_window = &tmp_window;
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tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
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tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
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tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
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tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
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tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
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tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
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tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
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tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
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}
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if (!dc_stream_configure_crc(stream_state->ctx->dc,
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stream_state, NULL, enable, enable)) {
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stream_state, crc_window, enable, enable)) {
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ret = -EINVAL;
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goto unlock;
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}
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@ -47,6 +47,9 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
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/* amdgpu_dm_crc.c */
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#ifdef CONFIG_DEBUG_FS
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bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
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bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
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struct dm_crtc_state *dm_old_crtc_state);
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int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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struct dm_crtc_state *dm_crtc_state,
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enum amdgpu_dm_pipe_crc_source source);
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@ -3259,6 +3259,9 @@ void core_link_enable_stream(
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#endif
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dc->hwss.enable_audio_stream(pipe_ctx);
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/* turn off otg test pattern if enable */
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