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riscv: dts: sophgo: Add i2c device support for sg2042

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The i2c ip of sg2042 is a standard Synopsys i2c ip, which is already
supported by the mainline kernel.

Add i2c device node for sg2042.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB49530E59974AF0FCA4FAB6DBBBB72@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Inochi Amaoto 2024-07-29 10:13:34 +08:00 committed by Chen Wang
parent 5d9e6bc82b
commit c8eb04aecd
1 changed files with 52 additions and 0 deletions
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52
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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@ -47,6 +47,58 @@
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
ranges; ranges;
i2c0: i2c@7030005000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C0>;
status = "disabled";
};
i2c1: i2c@7030006000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C1>;
status = "disabled";
};
i2c2: i2c@7030007000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30007000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C2>;
status = "disabled";
};
i2c3: i2c@7030008000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30008000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C3>;
status = "disabled";
};
pllclk: clock-controller@70300100c0 { pllclk: clock-controller@70300100c0 {
compatible = "sophgo,sg2042-pll"; compatible = "sophgo,sg2042-pll";
reg = <0x70 0x300100c0 0x0 0x40>; reg = <0x70 0x300100c0 0x0 0x40>;