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wifi: rtl8xxxu: Simplify setting the initial gain

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The goal of writing 0x6954341e / 0x6955341e to REG_OFDM0_XA_AGC_CORE1
appears to be setting the initial gain, which is stored in bits 0..6.
Bits 7..31 are the same as what the phy init tables write.

Modify only bits 0..6 so that we don't have to care about the values
of the others. This way we don't have to add another "else if" for the
RTL8192FU.

Why we need to change the initial gain from the default 0x20 to 0x1e?
Not sure. Some of the vendor drivers change it to 0x1e before scanning
and then restore it to the original value after.

Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Reviewed-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/cf91ca69-70e3-4c20-c0b1-e59d452356a1@gmail.com
This commit is contained in:
Bitterblue Smith 2023-04-17 20:08:20 +03:00 committed by Kalle Valo
parent cd85c8b059
commit c8bc376027
1 changed files with 2 additions and 4 deletions
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6
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
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@ -7034,10 +7034,8 @@ exit:
rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
if (priv->rtl_chip == RTL8188E) rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,
rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6955341e); OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);
else
rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
return ret; return ret;