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i.MX drivers update for 5.18:
- Drop LS1021A device check from soc-imx driver as it's unneeded since commit commit4ebd29f916("soc: imx: Register SoC device only on i.MX boards"). - Add support for power domains provided by the VPU blk-ctrl on the i.MX8MQ. - Add resource owner management API which will be used to check whether M4 is under control of Linux. - Add VPU MU resources support into SCU power domain driver. - Support DT overlay for WEIM bus driver with OF reconfiguration notifier handler. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUirsUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM54UQf/UzYym4Y/Clur4F7xh4XodaP6Y2fF M7DJUcE7rkI4jHCASnyh7NwSdqLCBiXOa6GVMpagELG8qoMYV/Gcwdt2Q60tn8TM ASADkSKobjDF7hywQpGQL9808QTKglRwgVBnTgeKaUrjE1Lw0gebgM9qoisrUzjk wwQxnUdyNxkeCOw5743z28H+lJmC8j3EecD+mjN6DiqCJYIMacQQ3+7S0pyHq2ii TdaV0oi4ApannwlxcguqYDDgwX7VXxnguPmGVIHc8Pq+zqmbCTfcaUbRTwlYX4PK 5CCb+2sN8v0MYxKH5elYuUoMQeTZ2w7IeK99JDoCNueNbIbK6G7wndHfdQ== =m1lO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/kEACgkQmmx57+YA GNnOZQ//U4XOr+yZA5csefH0z3LDKuQBFVuM6w2pXw8sdcC84X4BFlRjJNeam8jT LqS5t69nWJaN/1qny8MeX5lBk7rqomRs3iVizKR6AP6EsKw39F8i89U0eD7ePXiQ dKkio4lL8w4WuOnNwoaY7eElh+jP+gYftnv8GVAmjxSJkjBTAM2HtQjFdg+G+5kn UOCkdq6/goyvA54oq+MWfn+sSXHOyPYN4kyndb87sWnTNoLeGzklFIm4uTeG3A+e 716vS9sm1CZZrSB2FLxMffY/VDgQBLFZPU/fqgbetVQA2+cyQH+YHPSFdHs+eTje KqtjuKIRs1zuMy2jnSDS7KIj9c9JtNJtJJG2a0bskom4z3lG/yXfnmbQEJgj82jI T54YwM4h5MQlzznduQcyk3F3vhQssqauBjC/KIIw4TpP4qlDOpFls+v+8KNtDaDK Znk5j3gzX4H2DvWxE3OoQePCCx7LKvM5pgRYZffrHvaVIFUlAykDhjNuGI05+Wdh uAXeTqFmWxQ9iPy5M3zQh1i3cYIKhEE+4plO7lRFDbFny4ylQDcKR+fKtVmDzmN+ JcYHpdcy9PTzGIf/9qiDQHSEGcvalPBwlGy7kUTewT0t+yvUTqG1EJz8ndgQL7f6 4wCHShGVTD55gp2OLszeFsvHae5UoPvDornryNS9pB1KCAbzbSg= =N5wZ -----END PGP SIGNATURE----- Merge tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.18: - Drop LS1021A device check from soc-imx driver as it's unneeded since commit commit4ebd29f916("soc: imx: Register SoC device only on i.MX boards"). - Add support for power domains provided by the VPU blk-ctrl on the i.MX8MQ. - Add resource owner management API which will be used to check whether M4 is under control of Linux. - Add VPU MU resources support into SCU power domain driver. - Support DT overlay for WEIM bus driver with OF reconfiguration notifier handler. * tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: bus: imx-weim: add DT overlay support for WEIM bus firmware: imx: scu-pd: imx8q: add vpu mu resources firmware: imx: add get resource owner api soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains soc: imx: Remove Layerscape check Link: https://lore.kernel.org/r/20220222075226.160187-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c8812c2a08
@ -64,6 +64,11 @@ struct cs_timing_state {
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struct cs_timing cs[MAX_CS_COUNT];
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};
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struct weim_priv {
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void __iomem *base;
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struct cs_timing_state timing_state;
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};
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static const struct of_device_id weim_id_table[] = {
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/* i.MX1/21 */
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{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
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@ -128,21 +133,26 @@ err:
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}
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/* Parse and set the timing for this device. */
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static int weim_timing_setup(struct device *dev,
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struct device_node *np, void __iomem *base,
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const struct imx_weim_devtype *devtype,
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struct cs_timing_state *ts)
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static int weim_timing_setup(struct device *dev, struct device_node *np,
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const struct imx_weim_devtype *devtype)
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{
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u32 cs_idx, value[MAX_CS_REGS_COUNT];
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int i, ret;
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int reg_idx, num_regs;
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struct cs_timing *cst;
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struct weim_priv *priv;
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struct cs_timing_state *ts;
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void __iomem *base;
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if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
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return -EINVAL;
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if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
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return -EINVAL;
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priv = dev_get_drvdata(dev);
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base = priv->base;
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ts = &priv->timing_state;
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ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
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value, devtype->cs_regs_count);
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if (ret)
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@ -189,14 +199,15 @@ static int weim_timing_setup(struct device *dev,
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return 0;
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}
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static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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static int weim_parse_dt(struct platform_device *pdev)
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{
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const struct of_device_id *of_id = of_match_device(weim_id_table,
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&pdev->dev);
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const struct imx_weim_devtype *devtype = of_id->data;
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struct device_node *child;
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int ret, have_child = 0;
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struct cs_timing_state ts = {};
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struct weim_priv *priv;
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void __iomem *base;
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u32 reg;
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if (devtype == &imx50_weim_devtype) {
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@ -205,6 +216,9 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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return ret;
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}
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priv = dev_get_drvdata(&pdev->dev);
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base = priv->base;
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if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
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if (devtype->wcr_bcm) {
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reg = readl(base + devtype->wcr_offset);
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@ -229,7 +243,7 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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}
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
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ret = weim_timing_setup(&pdev->dev, child, devtype);
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if (ret)
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dev_warn(&pdev->dev, "%pOF set timing failed.\n",
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child);
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@ -248,17 +262,25 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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static int weim_probe(struct platform_device *pdev)
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{
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struct weim_priv *priv;
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struct resource *res;
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struct clk *clk;
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void __iomem *base;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* get the resource */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->base = base;
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dev_set_drvdata(&pdev->dev, priv);
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/* get the clock */
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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@ -269,7 +291,7 @@ static int weim_probe(struct platform_device *pdev)
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return ret;
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/* parse the device node */
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ret = weim_parse_dt(pdev, base);
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ret = weim_parse_dt(pdev);
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if (ret)
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clk_disable_unprepare(clk);
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else
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@ -278,6 +300,81 @@ static int weim_probe(struct platform_device *pdev)
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return ret;
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}
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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static int of_weim_notify(struct notifier_block *nb, unsigned long action,
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void *arg)
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{
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const struct imx_weim_devtype *devtype;
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struct of_reconfig_data *rd = arg;
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const struct of_device_id *of_id;
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struct platform_device *pdev;
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int ret = NOTIFY_OK;
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switch (of_reconfig_get_state_change(action, rd)) {
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case OF_RECONFIG_CHANGE_ADD:
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of_id = of_match_node(weim_id_table, rd->dn->parent);
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if (!of_id)
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return NOTIFY_OK; /* not for us */
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devtype = of_id->data;
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pdev = of_find_device_by_node(rd->dn->parent);
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if (!pdev) {
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pr_err("%s: could not find platform device for '%pOF'\n",
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__func__, rd->dn->parent);
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return notifier_from_errno(-EINVAL);
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}
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if (weim_timing_setup(&pdev->dev, rd->dn, devtype))
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dev_warn(&pdev->dev,
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"Failed to setup timing for '%pOF'\n", rd->dn);
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if (!of_node_check_flag(rd->dn, OF_POPULATED)) {
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if (!of_platform_device_create(rd->dn, NULL, &pdev->dev)) {
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dev_err(&pdev->dev,
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"Failed to create child device '%pOF'\n",
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rd->dn);
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ret = notifier_from_errno(-EINVAL);
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}
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}
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platform_device_put(pdev);
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break;
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case OF_RECONFIG_CHANGE_REMOVE:
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if (!of_node_check_flag(rd->dn, OF_POPULATED))
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return NOTIFY_OK; /* device already destroyed */
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of_id = of_match_node(weim_id_table, rd->dn->parent);
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if (!of_id)
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return NOTIFY_OK; /* not for us */
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pdev = of_find_device_by_node(rd->dn);
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if (!pdev) {
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dev_err(&pdev->dev,
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"Could not find platform device for '%pOF'\n",
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rd->dn);
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ret = notifier_from_errno(-EINVAL);
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} else {
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of_platform_device_destroy(&pdev->dev, NULL);
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platform_device_put(pdev);
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}
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break;
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default:
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break;
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}
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return ret;
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}
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struct notifier_block weim_of_notifier = {
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.notifier_call = of_weim_notify,
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};
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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static struct platform_driver weim_driver = {
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.driver = {
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.name = "imx-weim",
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@ -285,7 +382,27 @@ static struct platform_driver weim_driver = {
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},
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.probe = weim_probe,
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};
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module_platform_driver(weim_driver);
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static int __init weim_init(void)
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{
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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WARN_ON(of_reconfig_notifier_register(&weim_of_notifier));
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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return platform_driver_register(&weim_driver);
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}
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module_init(weim_init);
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static void __exit weim_exit(void)
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{
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#if IS_ENABLED(CONFIG_OF_DYNAMIC)
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of_reconfig_notifier_unregister(&weim_of_notifier);
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#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */
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return platform_driver_unregister(&weim_driver);
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}
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module_exit(weim_exit);
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MODULE_AUTHOR("Freescale Semiconductor Inc.");
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MODULE_DESCRIPTION("i.MX EIM Controller Driver");
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@ -43,3 +43,48 @@ bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource)
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return hdr->func;
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}
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EXPORT_SYMBOL(imx_sc_rm_is_resource_owned);
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struct imx_sc_msg_rm_get_resource_owner {
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struct imx_sc_rpc_msg hdr;
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union {
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struct {
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u16 resource;
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} req;
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struct {
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u8 val;
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} resp;
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} data;
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} __packed __aligned(4);
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/*
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* This function get @resource partition number
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*
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* @param[in] ipc IPC handle
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* @param[in] resource resource the control is associated with
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* @param[out] pt pointer to return the partition number
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*
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* @return Returns 0 for success and < 0 for errors.
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*/
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int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt)
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{
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struct imx_sc_msg_rm_get_resource_owner msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_RM;
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hdr->func = IMX_SC_RM_FUNC_GET_RESOURCE_OWNER;
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hdr->size = 2;
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msg.data.req.resource = resource;
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ret = imx_scu_call_rpc(ipc, &msg, true);
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if (ret)
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return ret;
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if (pt)
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*pt = msg.data.resp.val;
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return 0;
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}
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EXPORT_SYMBOL(imx_sc_rm_get_resource_owner);
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@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
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{ "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 },
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{ "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 },
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{ "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 },
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{ "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 },
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{ "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 },
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{ "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 },
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{ "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 },
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/* GPU SS */
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{ "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
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@ -15,6 +15,7 @@
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#define BLK_SFT_RSTN 0x0
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#define BLK_CLK_EN 0x4
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@ -589,6 +590,68 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
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.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
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};
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static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
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power_nb);
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if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
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return NOTIFY_OK;
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/*
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* The ADB in the VPUMIX domain has no separate reset and clock
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* enable bits, but is ungated and reset together with the VPUs. The
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* reset and clock enable inputs to the ADB is a logical OR of the
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* VPU bits. In order to set the G2 fuse bits, the G2 clock must
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* also be enabled.
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*/
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));
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regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));
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if (action == GENPD_NOTIFY_ON) {
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/*
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* On power up we have no software backchannel to the GPC to
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* wait for the ADB handshake to happen, so we just delay for a
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* bit. On power down the GPC driver waits for the handshake.
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*/
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udelay(5);
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/* set "fuse" bits to enable the VPUs */
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regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
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regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
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regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
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}
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return NOTIFY_OK;
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}
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static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
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[IMX8MQ_VPUBLK_PD_G1] = {
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.name = "vpublk-g1",
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.clk_names = (const char *[]){ "g1", },
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.num_clks = 1,
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.gpc_name = "g1",
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.rst_mask = BIT(1),
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.clk_mask = BIT(1),
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},
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[IMX8MQ_VPUBLK_PD_G2] = {
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.name = "vpublk-g2",
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.clk_names = (const char *[]){ "g2", },
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.num_clks = 1,
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.gpc_name = "g2",
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.rst_mask = BIT(0),
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.clk_mask = BIT(0),
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},
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};
|
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static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {
|
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.max_reg = 0x14,
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.power_notifier_fn = imx8mq_vpu_power_notifier,
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.domains = imx8mq_vpu_blk_ctl_domain_data,
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.num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),
|
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};
|
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|
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static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
|
||||
{
|
||||
.compatible = "fsl,imx8mm-vpu-blk-ctrl",
|
||||
@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
|
||||
}, {
|
||||
.compatible = "fsl,imx8mn-disp-blk-ctrl",
|
||||
.data = &imx8mn_disp_blk_ctl_dev_data
|
||||
}, {
|
||||
.compatible = "fsl,imx8mq-vpu-blk-ctrl",
|
||||
.data = &imx8mq_vpu_blk_ctl_dev_data
|
||||
}, {
|
||||
/* Sentinel */
|
||||
}
|
||||
|
||||
@ -40,9 +40,6 @@ static int __init imx_soc_device_init(void)
|
||||
if (!__mxc_cpu_type)
|
||||
return 0;
|
||||
|
||||
if (of_machine_is_compatible("fsl,ls1021a"))
|
||||
return 0;
|
||||
|
||||
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
||||
if (!soc_dev_attr)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -18,4 +18,7 @@
|
||||
#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
|
||||
#define IMX8M_POWER_DOMAIN_PCIE2 10
|
||||
|
||||
#define IMX8MQ_VPUBLK_PD_G1 0
|
||||
#define IMX8MQ_VPUBLK_PD_G2 1
|
||||
|
||||
#endif
|
||||
|
||||
@ -59,11 +59,16 @@ enum imx_sc_rm_func {
|
||||
|
||||
#if IS_ENABLED(CONFIG_IMX_SCU)
|
||||
bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource);
|
||||
int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt);
|
||||
#else
|
||||
static inline bool
|
||||
imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
static inline int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user