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Third Round of Renesas SH SCI Updates for v3.14

Browse Source 
* Add Device Tree Support
 * Remove platform data mapbase and irqs fields
 * Remove platform data scbrr_algo_id field
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Merge tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

From Simon Horman:
Third Round of Renesas SH SCI Updates for v3.14

* Add Device Tree Support
* Remove platform data mapbase and irqs fields
* Remove platform data scbrr_algo_id field

* tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  serial: sh-sci: Add OF support
  serial: sh-sci: Add device tree bindings documentation
  serial: sh-sci: Remove platform data mapbase and irqs fields
  serial: sh-sci: Remove platform data scbrr_algo_id field

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-01-02 10:57:05 -08:00
commit c7fed591a6
45 changed files with 1162 additions and 1149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt Normal file
View File

@ -0,0 +1,46 @@
* Renesas SH-Mobile Serial Communication Interface
Required properties:
- compatible: Must contain one of the following:
- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
- "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
- "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
- "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
- "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
- "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
- "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
- "renesas,scif" for generic SCIF compatible UART.
- "renesas,scifa" for generic SCIFA compatible UART.
- "renesas,scifb" for generic SCIFB compatible UART.
- "renesas,hscif" for generic HSCIF compatible UART.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first followed by the
generic version.
- reg: Base address and length of the I/O registers used by the UART.
- interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
- clocks: Must contain a phandle and clock-specifier pair for each entry
in clock-names.
- clock-names: Must contain "sci_ick" for the SCIx UART interface clock.
Note: Each enabled SCIx UART should have an alias correctly numbered in the
"aliases" node.
Example:
aliases {
serial0 = &scifa0;
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
reg = <0 0xe6c40000 0 64>;
interrupt-parent = <&gic>;
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
clock-names = "sci_ick";
};

14
arch/arm/Kconfig
View File

@ -644,8 +644,9 @@ config ARCH_MSM
stack and controls some vital subsystems
(clock and power control, etc).
config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
config ARCH_SHMOBILE_LEGACY
bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
select ARCH_SHMOBILE
select ARM_PATCH_PHYS_VIRT
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
@ -660,7 +661,8 @@ config ARCH_SHMOBILE
select PM_GENERIC_DOMAINS if PM
select SPARSE_IRQ
help
Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
a non-multiplatform kernel.
config ARCH_RPC
bool "RiscPC"
@ -1614,7 +1616,7 @@ config HZ_FIXED
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
ARCH_S5PV210 || ARCH_EXYNOS4
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
default 0
choice
@ -1799,8 +1801,8 @@ config ARCH_WANT_GENERAL_HUGETLB
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE
range 11 64 if ARCH_SHMOBILE
int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
range 11 64 if ARCH_SHMOBILE_LEGACY
default "12" if SOC_AM33XX
default "9" if SA1111
default "11"

1
arch/arm/Makefile
View File

@ -190,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
machine-$(CONFIG_ARCH_SIRF) += prima2
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti

2
arch/arm/boot/compressed/Makefile
View File

@ -64,7 +64,7 @@ else
endif
endif
ifeq ($(CONFIG_ARCH_SHMOBILE),y)
ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
OBJS += head-shmobile.o
endif

2
arch/arm/boot/dts/Makefile
View File

@ -217,7 +217,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \

2
arch/arm/configs/ape6evm_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLOCK is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A73A4=y
CONFIG_MACH_APE6EVM=y
# CONFIG_ARM_THUMB is not set

2
arch/arm/configs/armadillo800eva_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7740=y
CONFIG_MACH_ARMADILLO800EVA=y
# CONFIG_SH_TIMER_TMU is not set

2
arch/arm/configs/bockw_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7778=y
CONFIG_MACH_BOCKW=y
CONFIG_MEMORY_START=0x60000000

2
arch/arm/configs/koelsch_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLOCK is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7791=y
CONFIG_MACH_KOELSCH=y
# CONFIG_SWP_EMULATE is not set

2
arch/arm/configs/kzm9d_defconfig
View File

@ -13,7 +13,7 @@ CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_EMEV2=y
CONFIG_MACH_KZM9D=y
CONFIG_MEMORY_START=0x40000000

2
arch/arm/configs/kzm9g_defconfig
View File

@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH73A0=y
CONFIG_MACH_KZM9G=y
CONFIG_MEMORY_START=0x41000000

2
arch/arm/configs/lager_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7790=y
CONFIG_MACH_LAGER=y
# CONFIG_SH_TIMER_TMU is not set

2
arch/arm/configs/mackerel_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH7372=y
CONFIG_MACH_MACKEREL=y
CONFIG_MEMORY_SIZE=0x10000000

2
arch/arm/configs/marzen_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE=y
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7779=y
CONFIG_MACH_MARZEN=y
CONFIG_MEMORY_START=0x60000000

24
arch/arm/mach-shmobile/Kconfig
View File

@ -1,6 +1,10 @@
config ARCH_SHMOBILE
bool
config ARCH_SHMOBILE_MULTI
bool "SH-Mobile Series" if ARCH_MULTI_V7
depends on MMU
select ARCH_SHMOBILE
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
select HAVE_SMP
select ARM_GIC
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select NO_IOPORT
select PINCTRL
select ARCH_REQUIRE_GPIOLIB
@ -30,7 +35,7 @@ config MACH_KZM9D
comment "SH-Mobile System Configuration"
endif
if ARCH_SHMOBILE
if ARCH_SHMOBILE_LEGACY
comment "SH-Mobile System Type"
@ -92,23 +97,31 @@ config ARCH_R8A7790
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select RENESAS_IRQC
config ARCH_R8A7791
bool "R-Car M2 (R8A77910)"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select RENESAS_IRQC
config ARCH_EMEV2
bool "Emma Mobile EV2"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select MIGHT_HAVE_PCI
select USE_OF
select AUTO_ZRELADDR
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select CPU_V7
select SH_CLK_CPG
@ -230,12 +243,7 @@ config MACH_KOELSCH
bool "Koelsch board"
depends on ARCH_R8A7791
select USE_OF
config MACH_KZM9D
bool "KZM9D board"
depends on ARCH_EMEV2
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
select MICREL_PHY if SH_ETH
config MACH_KZM9G
bool "KZM-A9-GT board"
@ -274,7 +282,7 @@ source "drivers/sh/Kconfig"
endif
if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI
if ARCH_SHMOBILE
menu "Timer and clock configuration"

1
arch/arm/mach-shmobile/Makefile
View File

@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
endif

1
arch/arm/mach-shmobile/Makefile.boot
View File

@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000
loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000

1
arch/arm/mach-shmobile/board-bockw.c
View File

@ -25,6 +25,7 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mtd/partitions.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/camera-rcar.h>
#include <linux/platform_data/usb-rcar-phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>

92
arch/arm/mach-shmobile/board-kzm9d.c
View File

@ -1,92 +0,0 @@
/*
* kzm9d board support
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};
/* Ether */
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x20000000,
.end = 0x2000ffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = EMEV2_GPIO_IRQ(1),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
},
};
static struct smsc911x_platform_config smsc911x_platdata = {
.flags = SMSC911X_USE_32BIT,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
};
static struct platform_device smsc91x_device = {
.name = "smsc911x",
.id = -1,
.dev = {
.platform_data = &smsc911x_platdata,
},
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
};
static struct platform_device *kzm9d_devices[] __initdata = {
&smsc91x_device,
};
void __init kzm9d_add_standard_devices(void)
{
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
emev2_add_standard_devices();
platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
}
static const char *kzm9d_boards_compat_dt[] __initdata = {
"renesas,kzm9d",
NULL,
};
DT_MACHINE_START(KZM9D_DT, "kzm9d")
.smp = smp_ops(emev2_smp_ops),
.map_io = emev2_map_io,
.init_early = emev2_init_delay,
.init_machine = kzm9d_add_standard_devices,
.init_late = shmobile_init_late,
.dt_compat = kzm9d_boards_compat_dt,
MACHINE_END

8
arch/arm/mach-shmobile/clock-r7s72100.c
View File

@ -27,6 +27,7 @@
#define FRQCR2 0xfcfe0014
#define STBCR3 0xfcfe0420
#define STBCR4 0xfcfe0424
#define STBCR9 0xfcfe0438
#define PLL_RATE 30
@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
| CLK_ENABLE_ON_INIT),
};
enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
enum { MSTP97, MSTP96, MSTP95, MSTP94,
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
MSTP33, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
[MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */

1
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -585,6 +585,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),

31
arch/arm/mach-shmobile/clock-r8a7778.c
View File

@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
};
enum {
MSTP531, MSTP530,
MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
MSTP331,
MSTP323, MSTP322, MSTP321,
MSTP311, MSTP310,
@ -129,6 +131,15 @@ enum {
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
[MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
[MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
[MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
[MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
[MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
[MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
[MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
[MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
[MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
};
void __init r8a7778_clock_init(void)

11
arch/arm/mach-shmobile/clock-r8a7779.c
View File

@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */
CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
};

62
arch/arm/mach-shmobile/clock-r8a7790.c
View File

@ -53,6 +53,7 @@
#define SMSTPCR7 0xe615014c
#define SMSTPCR8 0xe6150990
#define SMSTPCR9 0xe6150994
#define SMSTPCR10 0xe6150998
#define SDCKCR 0xE6150074
#define SD2CKCR 0xE6150078
@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = {
/* MSTP */
enum {
MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
MSTP931, MSTP930, MSTP929, MSTP928,
MSTP917,
MSTP813,
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
MSTP717, MSTP716,
MSTP704,
MSTP522,
MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@ -194,10 +199,22 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
[MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
[MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
[MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
[MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
[MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
[MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
[MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
[MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
[MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
[MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
[MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
[MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
[MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
[MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
[MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
/* MSTP */
CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@ -278,10 +292,15 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP931]),
CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP930]),
CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP929]),
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP928]),
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
@ -296,6 +315,27 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
/* ICK */
CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
};
#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void)
R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
break;
case MD(14):
R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
break;
case MD(13) | MD(14):
R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
break;
}

17
arch/arm/mach-shmobile/clock-r8a7791.c
View File

@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
static struct clk *main_clks[] = {
&extal_clk,
@ -116,12 +117,15 @@ static struct clk *main_clks[] = {
&rclk_clk,
&mp_clk,
&cp_clk,
&zx_clk,
};
/* MSTP */
enum {
MSTP721, MSTP720,
MSTP813,
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
MSTP719, MSTP718, MSTP715, MSTP714,
MSTP522,
MSTP216, MSTP207, MSTP206,
MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
MSTP124,
@ -129,12 +133,17 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
[MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
[MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
[MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("peripheral_clk", &hp_clk),
/* MSTP */
CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
};
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \

1
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -658,6 +658,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */

5
arch/arm/mach-shmobile/include/mach/emev2.h
View File

@ -3,12 +3,7 @@
extern void emev2_map_io(void);
extern void emev2_init_delay(void);
extern void emev2_add_standard_devices(void);
extern void emev2_clock_init(void);
#define EMEV2_GPIO_BASE 200
#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
extern struct smp_operations emev2_smp_ops;
#endif /* __ASM_EMEV2_H__ */

39
arch/arm/mach-shmobile/include/mach/r8a7778.h
View File

@ -20,13 +20,50 @@
#define __ASM_R8A7778_H__
#include <linux/sh_eth.h>
#include <linux/platform_data/camera-rcar.h>
/* HPB-DMA slave IDs */
enum {
HPBDMA_SLAVE_DUMMY,
HPBDMA_SLAVE_SDHI0_TX,
HPBDMA_SLAVE_SDHI0_RX,
HPBDMA_SLAVE_SSI0_TX,
HPBDMA_SLAVE_SSI0_RX,
HPBDMA_SLAVE_SSI1_TX,
HPBDMA_SLAVE_SSI1_RX,
HPBDMA_SLAVE_SSI2_TX,
HPBDMA_SLAVE_SSI2_RX,
HPBDMA_SLAVE_SSI3_TX,
HPBDMA_SLAVE_SSI3_RX,
HPBDMA_SLAVE_SSI4_TX,
HPBDMA_SLAVE_SSI4_RX,
HPBDMA_SLAVE_SSI5_TX,
HPBDMA_SLAVE_SSI5_RX,
HPBDMA_SLAVE_SSI6_TX,
HPBDMA_SLAVE_SSI6_RX,
HPBDMA_SLAVE_SSI7_TX,
HPBDMA_SLAVE_SSI7_RX,
HPBDMA_SLAVE_SSI8_TX,
HPBDMA_SLAVE_SSI8_RX,
HPBDMA_SLAVE_HPBIF0_TX,
HPBDMA_SLAVE_HPBIF0_RX,
HPBDMA_SLAVE_HPBIF1_TX,
HPBDMA_SLAVE_HPBIF1_RX,
HPBDMA_SLAVE_HPBIF2_TX,
HPBDMA_SLAVE_HPBIF2_RX,
HPBDMA_SLAVE_HPBIF3_TX,
HPBDMA_SLAVE_HPBIF3_RX,
HPBDMA_SLAVE_HPBIF4_TX,
HPBDMA_SLAVE_HPBIF4_RX,
HPBDMA_SLAVE_HPBIF5_TX,
HPBDMA_SLAVE_HPBIF5_RX,
HPBDMA_SLAVE_HPBIF6_TX,
HPBDMA_SLAVE_HPBIF6_RX,
HPBDMA_SLAVE_HPBIF7_TX,
HPBDMA_SLAVE_HPBIF7_RX,
HPBDMA_SLAVE_HPBIF8_TX,
HPBDMA_SLAVE_HPBIF8_RX,
HPBDMA_SLAVE_USBFUNC_TX,
HPBDMA_SLAVE_USBFUNC_RX,
};
extern void r8a7778_add_standard_devices(void);

1
arch/arm/mach-shmobile/include/mach/r8a7791.h
View File

@ -4,6 +4,7 @@
void r8a7791_add_standard_devices(void);
void r8a7791_add_dt_devices(void);
void r8a7791_clock_init(void);
void r8a7791_pinmux_init(void);
void r8a7791_init_early(void);
extern struct smp_operations r8a7791_smp_ops;

163
arch/arm/mach-shmobile/setup-emev2.c
View File

@ -16,24 +16,15 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-em.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/emev2.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
static struct map_desc emev2_io_desc[] __initdata = {
#ifdef CONFIG_SMP
@ -52,150 +43,20 @@ void __init emev2_map_io(void)
iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
}
/* UART */
static struct resource uart0_resources[] = {
DEFINE_RES_MEM(0xe1020000, 0x38),
DEFINE_RES_IRQ(40),
};
static struct resource uart1_resources[] = {
DEFINE_RES_MEM(0xe1030000, 0x38),
DEFINE_RES_IRQ(41),
};
static struct resource uart2_resources[] = {
DEFINE_RES_MEM(0xe1040000, 0x38),
DEFINE_RES_IRQ(42),
};
static struct resource uart3_resources[] = {
DEFINE_RES_MEM(0xe1050000, 0x38),
DEFINE_RES_IRQ(43),
};
#define emev2_register_uart(idx) \
platform_device_register_simple("serial8250-em", idx, \
uart##idx##_resources, \
ARRAY_SIZE(uart##idx##_resources))
/* STI */
static struct resource sti_resources[] = {
DEFINE_RES_MEM(0xe0180000, 0x54),
DEFINE_RES_IRQ(157),
};
#define emev2_register_sti() \
platform_device_register_simple("em_sti", 0, \
sti_resources, \
ARRAY_SIZE(sti_resources))
/* GIO */
static struct gpio_em_config gio0_config = {
.gpio_base = 0,
.irq_base = EMEV2_GPIO_IRQ(0),
.number_of_pins = 32,
};
static struct resource gio0_resources[] = {
DEFINE_RES_MEM(0xe0050000, 0x2c),
DEFINE_RES_MEM(0xe0050040, 0x20),
DEFINE_RES_IRQ(99),
DEFINE_RES_IRQ(100),
};
static struct gpio_em_config gio1_config = {
.gpio_base = 32,
.irq_base = EMEV2_GPIO_IRQ(32),
.number_of_pins = 32,
};
static struct resource gio1_resources[] = {
DEFINE_RES_MEM(0xe0050080, 0x2c),
DEFINE_RES_MEM(0xe00500c0, 0x20),
DEFINE_RES_IRQ(101),
DEFINE_RES_IRQ(102),
};
static struct gpio_em_config gio2_config = {
.gpio_base = 64,
.irq_base = EMEV2_GPIO_IRQ(64),
.number_of_pins = 32,
};
static struct resource gio2_resources[] = {
DEFINE_RES_MEM(0xe0050100, 0x2c),
DEFINE_RES_MEM(0xe0050140, 0x20),
DEFINE_RES_IRQ(103),
DEFINE_RES_IRQ(104),
};
static struct gpio_em_config gio3_config = {
.gpio_base = 96,
.irq_base = EMEV2_GPIO_IRQ(96),
.number_of_pins = 32,
};
static struct resource gio3_resources[] = {
DEFINE_RES_MEM(0xe0050180, 0x2c),
DEFINE_RES_MEM(0xe00501c0, 0x20),
DEFINE_RES_IRQ(105),
DEFINE_RES_IRQ(106),
};
static struct gpio_em_config gio4_config = {
.gpio_base = 128,
.irq_base = EMEV2_GPIO_IRQ(128),
.number_of_pins = 31,
};
static struct resource gio4_resources[] = {
DEFINE_RES_MEM(0xe0050200, 0x2c),
DEFINE_RES_MEM(0xe0050240, 0x20),
DEFINE_RES_IRQ(107),
DEFINE_RES_IRQ(108),
};
#define emev2_register_gio(idx) \
platform_device_register_resndata(&platform_bus, "em_gio", \
idx, gio##idx##_resources, \
ARRAY_SIZE(gio##idx##_resources), \
&gio##idx##_config, \
sizeof(struct gpio_em_config))
static struct resource pmu_resources[] = {
DEFINE_RES_IRQ(152),
DEFINE_RES_IRQ(153),
};
#define emev2_register_pmu() \
platform_device_register_simple("arm-pmu", -1, \
pmu_resources, \
ARRAY_SIZE(pmu_resources))
void __init emev2_add_standard_devices(void)
{
if (!IS_ENABLED(CONFIG_COMMON_CLK))
emev2_clock_init();
emev2_register_uart(0);
emev2_register_uart(1);
emev2_register_uart(2);
emev2_register_uart(3);
emev2_register_sti();
emev2_register_gio(0);
emev2_register_gio(1);
emev2_register_gio(2);
emev2_register_gio(3);
emev2_register_gio(4);
emev2_register_pmu();
}
void __init emev2_init_delay(void)
{
shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
}
#ifdef CONFIG_USE_OF
static void __init emev2_add_standard_devices_dt(void)
{
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#else
emev2_clock_init();
#endif
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *emev2_boards_compat_dt[] __initdata = {
"renesas,emev2",
@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
.smp = smp_ops(emev2_smp_ops),
.map_io = emev2_map_io,
.init_early = emev2_init_delay,
.init_machine = emev2_add_standard_devices_dt,
.init_late = shmobile_init_late,
.dt_compat = emev2_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

82
arch/arm/mach-shmobile/setup-r7s72100.c
View File

@ -22,52 +22,76 @@
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r7s72100.h>
#include <asm/mach/arch.h>
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
#define R7S72100_SCIF(index, baseaddr, irq) \
static const struct plat_sci_port scif##index##_platform_data = { \
.type = PORT_SCIF, \
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
SCSCR_REIE, \
.mapbase = baseaddr, \
.irqs = { irq + 1, irq + 2, irq + 3, irq }, \
}
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq + 1), \
DEFINE_RES_IRQ(irq + 2), \
DEFINE_RES_IRQ(irq + 3), \
DEFINE_RES_IRQ(irq), \
} \
enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 };
R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
static const struct plat_sci_port scif[] __initconst = {
SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */
SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */
SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */
SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */
SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
#define r7s72100_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static struct sh_timer_config mtu2_0_platform_data __initdata = {
.name = "MTU2_0",
.timer_bit = 0,
.channel_offset = -0x80,
.clockevent_rating = 200,
};
static inline void r7s72100_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
static struct resource mtu2_0_resources[] __initdata = {
DEFINE_RES_MEM(0xfcff0300, 0x27),
DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
};
#define r7s72100_register_mtu2(idx) \
platform_device_register_resndata(&platform_bus, "sh_mtu2", \
idx, mtu2_##idx##_resources, \
ARRAY_SIZE(mtu2_##idx##_resources), \
&mtu2_##idx##_platform_data, \
sizeof(struct sh_timer_config))
void __init r7s72100_add_dt_devices(void)
{
r7s72100_register_scif(SCIF0);
r7s72100_register_scif(SCIF1);
r7s72100_register_scif(SCIF2);
r7s72100_register_scif(SCIF3);
r7s72100_register_scif(SCIF4);
r7s72100_register_scif(SCIF5);
r7s72100_register_scif(SCIF6);
r7s72100_register_scif(SCIF7);
r7s72100_register_scif(0);
r7s72100_register_scif(1);
r7s72100_register_scif(2);
r7s72100_register_scif(3);
r7s72100_register_scif(4);
r7s72100_register_scif(5);
r7s72100_register_scif(6);
r7s72100_register_scif(7);
r7s72100_register_mtu2(0);
}
void __init r7s72100_init_early(void)

68
arch/arm/mach-shmobile/setup-r8a73a4.c
View File

@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
ARRAY_SIZE(pfc_resources));
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scbrr_algo_id = SCBRR_ALGO_4, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
.scscr = _scscr, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define R8A73A4_SCIFA(index, baseaddr, irq) \
R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
index, baseaddr, irq)
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
#define R8A73A4_SCIFB(index, baseaddr, irq) \
R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
static const struct plat_sci_port scif[] = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
};
R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
static inline void r8a73a4_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define r8a73a4_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct renesas_irqc_config irqc0_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
void __init r8a73a4_add_dt_devices(void)
{
r8a73a4_register_scif(SCIFA0);
r8a73a4_register_scif(SCIFA1);
r8a73a4_register_scif(SCIFB0);
r8a73a4_register_scif(SCIFB1);
r8a73a4_register_scif(SCIFB2);
r8a73a4_register_scif(SCIFB3);
r8a73a4_register_scif(0);
r8a73a4_register_scif(1);
r8a73a4_register_scif(2);
r8a73a4_register_scif(3);
r8a73a4_register_scif(4);
r8a73a4_register_scif(5);
r8a7790_register_cmt(10);
}
@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = {
static struct resource dma_resources[] = {
DEFINE_RES_MEM(0xe6700020, 0x89e0),
DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
DEFINE_RES_IRQ(gic_spi(220)),
{
/* IRQ for channels 0-19 */
.start = gic_spi(200),

195
arch/arm/mach-shmobile/setup-r8a7740.c
View File

@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
},
};
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(100)),
};
/* SCIF */
#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(101)),
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(102)),
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(103)),
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(104)),
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(105)),
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFA6 */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(106)),
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
/* SCIFA7 */
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6cd0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = SCIx_IRQ_MUXED(gic_spi(107)),
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scifb_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = SCIx_IRQ_MUXED(gic_spi(108)),
};
static struct platform_device scifb_device = {
.name = "sh-sci",
.id = 8,
.dev = {
.platform_data = &scifb_platform_data,
},
};
R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
/* CMT */
static struct sh_timer_config cmt10_platform_data = {
@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
&scif5_device,
&scif6_device,
&scif7_device,
&scifb_device,
&scif8_device,
&cmt10_device,
};
@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
rmobile_add_device_to_domain("A3SP", &scif5_device);
rmobile_add_device_to_domain("A3SP", &scif6_device);
rmobile_add_device_to_domain("A3SP", &scif7_device);
rmobile_add_device_to_domain("A3SP", &scifb_device);
rmobile_add_device_to_domain("A3SP", &scif8_device);
rmobile_add_device_to_domain("A3SP", &i2c1_device);
}

166
arch/arm/mach-shmobile/setup-r8a7778.c
View File

@ -44,24 +44,31 @@
#include <asm/hardware/cache-l2x0.h>
/* SCIF */
#define SCIF_INFO(baseaddr, irq) \
{ \
.mapbase = baseaddr, \
#define R8A7778_SCIF(index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
.scbrr_algo_id = SCBRR_ALGO_2, \
.type = PORT_SCIF, \
.irqs = SCIx_IRQ_MUXED(irq), \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
static struct plat_sci_port scif_platform_data[] __initdata = {
SCIF_INFO(0xffe40000, gic_iid(0x66)),
SCIF_INFO(0xffe41000, gic_iid(0x67)),
SCIF_INFO(0xffe42000, gic_iid(0x68)),
SCIF_INFO(0xffe43000, gic_iid(0x69)),
SCIF_INFO(0xffe44000, gic_iid(0x6a)),
SCIF_INFO(0xffe45000, gic_iid(0x6b)),
};
R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
#define r8a7778_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
/* TMU */
static struct resource sh_tmu0_resources[] __initdata = {
@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
void __init r8a7778_add_dt_devices(void)
{
int i;
#ifdef CONFIG_CACHE_L2X0
void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
if (base) {
@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
}
#endif
for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
platform_device_register_data(&platform_bus, "sh-sci", i,
&scif_platform_data[i],
sizeof(struct plat_sci_port));
r8a7778_register_scif(0);
r8a7778_register_scif(1);
r8a7778_register_scif(2);
r8a7778_register_scif(3);
r8a7778_register_scif(4);
r8a7778_register_scif(5);
r8a7778_register_tmu(0);
r8a7778_register_tmu(1);
}
@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void)
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
#define HPBDMA_SSI(_id) \
{ \
.id = HPBDMA_SLAVE_SSI## _id ##_TX, \
.addr = 0xffd91008 + (_id * 0x40), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DMDL | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = _id + (_id << 8), \
.dma_ch = (28 + _id), \
}, { \
.id = HPBDMA_SLAVE_SSI## _id ##_RX, \
.addr = 0xffd9100c + (_id * 0x40), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SMDL | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = _id + (_id << 8), \
.dma_ch = (28 + _id), \
}
#define HPBDMA_HPBIF(_id) \
{ \
.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
.addr = 0xffda0000 + (_id * 0x1000), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DMDL | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = 0x1111, \
.dma_ch = (28 + _id), \
}, { \
.id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
.addr = 0xffda0000 + (_id * 0x1000), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SMDL | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = 0x1111, \
.dma_ch = (28 + _id), \
}
static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
{
.id = HPBDMA_SLAVE_SDHI0_TX,
@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
.port = 0x0D0C,
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
.dma_ch = 22,
}, {
.id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
.addr = 0xffe60018,
.dcr = HPB_DMAE_DCR_SPDS_32BIT |
HPB_DMAE_DCR_DMDL |
HPB_DMAE_DCR_DPDS_32BIT,
.port = 0x0000,
.dma_ch = 14,
}, {
.id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
.addr = 0xffe6001c,
.dcr = HPB_DMAE_DCR_SMDL |
HPB_DMAE_DCR_SPDS_32BIT |
HPB_DMAE_DCR_DPDS_32BIT,
.port = 0x0101,
.dma_ch = 15,
},
HPBDMA_SSI(0),
HPBDMA_SSI(1),
HPBDMA_SSI(2),
HPBDMA_SSI(3),
HPBDMA_SSI(4),
HPBDMA_SSI(5),
HPBDMA_SSI(6),
HPBDMA_SSI(7),
HPBDMA_SSI(8),
HPBDMA_HPBIF(0),
HPBDMA_HPBIF(1),
HPBDMA_HPBIF(2),
HPBDMA_HPBIF(3),
HPBDMA_HPBIF(4),
HPBDMA_HPBIF(5),
HPBDMA_HPBIF(6),
HPBDMA_HPBIF(7),
HPBDMA_HPBIF(8),
};
static const struct hpb_dmae_channel hpb_dmae_channels[] = {
HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
};
static struct hpb_dmae_pdata dma_platform_data __initdata = {

128
arch/arm/mach-shmobile/setup-r8a7779.c
View File

@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
ARRAY_SIZE(r8a7779_pinctrl_devices));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xffe40000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
};
/* SCIF */
#define R8A7779_SCIF(index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = PORT_SCIF, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xffe41000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xffe42000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xffe43000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xffe44000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xffe45000,
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
/* TMU */
static struct sh_timer_config tmu00_platform_data = {

131
arch/arm/mach-shmobile/setup-r8a7790.c
View File

@ -63,6 +63,27 @@ R8A7790_GPIO(5);
&r8a7790_gpio##idx##_platform_data, \
sizeof(r8a7790_gpio##idx##_platform_data))
static struct resource i2c_resources[] __initdata = {
/* I2C0 */
DEFINE_RES_MEM(0xE6508000, 0x40),
DEFINE_RES_IRQ(gic_spi(287)),
/* I2C1 */
DEFINE_RES_MEM(0xE6518000, 0x40),
DEFINE_RES_IRQ(gic_spi(288)),
/* I2C2 */
DEFINE_RES_MEM(0xE6530000, 0x40),
DEFINE_RES_IRQ(gic_spi(286)),
/* I2C3 */
DEFINE_RES_MEM(0xE6540000, 0x40),
DEFINE_RES_IRQ(gic_spi(290)),
};
#define r8a7790_register_i2c(idx) \
platform_device_register_simple( \
"i2c-rcar", idx, \
i2c_resources + (2 * idx), 2); \
void __init r8a7790_pinmux_init(void)
{
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
@ -73,63 +94,57 @@ void __init r8a7790_pinmux_init(void)
r8a7790_register_gpio(3);
r8a7790_register_gpio(4);
r8a7790_register_gpio(5);
r8a7790_register_i2c(0);
r8a7790_register_i2c(1);
r8a7790_register_i2c(2);
r8a7790_register_i2c(3);
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = _scscr, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define R8A7790_SCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define R8A7790_SCIFA(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
index, baseaddr, irq)
#define HSCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_6, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define R8A7790_SCIFB(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
HSCIF0, HSCIF1 };
#define R8A7790_HSCIF(index, baseaddr, irq) \
__R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
index, baseaddr, irq)
static const struct plat_sci_port scif[] __initconst = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
};
R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
static inline void r8a7790_register_scif(int idx)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
}
#define r8a7790_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct renesas_irqc_config irqc0_data __initconst = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
@ -182,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = {
void __init r8a7790_add_dt_devices(void)
{
r8a7790_register_scif(SCIFA0);
r8a7790_register_scif(SCIFA1);
r8a7790_register_scif(SCIFB0);
r8a7790_register_scif(SCIFB1);
r8a7790_register_scif(SCIFB2);
r8a7790_register_scif(SCIFA2);
r8a7790_register_scif(SCIF0);
r8a7790_register_scif(SCIF1);
r8a7790_register_scif(HSCIF0);
r8a7790_register_scif(HSCIF1);
r8a7790_register_scif(0);
r8a7790_register_scif(1);
r8a7790_register_scif(2);
r8a7790_register_scif(3);
r8a7790_register_scif(4);
r8a7790_register_scif(5);
r8a7790_register_scif(6);
r8a7790_register_scif(7);
r8a7790_register_scif(8);
r8a7790_register_scif(9);
r8a7790_register_cmt(00);
}

190
arch/arm/mach-shmobile/setup-r8a7791.c
View File

@ -22,6 +22,7 @@
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
@ -31,67 +32,102 @@
#include <mach/rcar-gen2.h>
#include <asm/mach/arch.h>
#define SCIF_COMMON(scif_type, baseaddr, irq) \
.type = scif_type, \
.mapbase = baseaddr, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.irqs = SCIx_IRQ_MUXED(irq)
#define SCIFA_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define SCIFB_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_4, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define SCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_2, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
#define HSCIF_DATA(index, baseaddr, irq) \
[index] = { \
SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
.scbrr_algo_id = SCBRR_ALGO_6, \
.scscr = SCSCR_RE | SCSCR_TE, \
}
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
static const struct plat_sci_port scif[] __initconst = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
static const struct resource pfc_resources[] __initconst = {
DEFINE_RES_MEM(0xe6060000, 0x250),
};
static inline void r8a7791_register_scif(int idx)
#define r8a7791_register_pfc() \
platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
ARRAY_SIZE(pfc_resources))
#define R8A7791_GPIO(idx, base, nr) \
static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
DEFINE_RES_MEM((base), 0x50), \
DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
}; \
\
static const struct gpio_rcar_config \
r8a7791_gpio##idx##_platform_data __initconst = { \
.gpio_base = 32 * (idx), \
.irq_base = 0, \
.number_of_pins = (nr), \
.pctl_name = "pfc-r8a7791", \
.has_both_edge_trigger = 1, \
}; \
R8A7791_GPIO(0, 0xe6050000, 32);
R8A7791_GPIO(1, 0xe6051000, 32);
R8A7791_GPIO(2, 0xe6052000, 32);
R8A7791_GPIO(3, 0xe6053000, 32);
R8A7791_GPIO(4, 0xe6054000, 32);
R8A7791_GPIO(5, 0xe6055000, 32);
R8A7791_GPIO(6, 0xe6055400, 32);
R8A7791_GPIO(7, 0xe6055800, 26);
#define r8a7791_register_gpio(idx) \
platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
r8a7791_gpio##idx##_resources, \
ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
&r8a7791_gpio##idx##_platform_data, \
sizeof(r8a7791_gpio##idx##_platform_data))
void __init r8a7791_pinmux_init(void)
{
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
sizeof(struct plat_sci_port));
r8a7791_register_pfc();
r8a7791_register_gpio(0);
r8a7791_register_gpio(1);
r8a7791_register_gpio(2);
r8a7791_register_gpio(3);
r8a7791_register_gpio(4);
r8a7791_register_gpio(5);
r8a7791_register_gpio(6);
r8a7791_register_gpio(7);
}
#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}
#define R8A7791_SCIF(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
#define R8A7791_SCIFA(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
#define R8A7791_SCIFB(index, baseaddr, irq) \
__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
#define r8a7791_register_scif(index) \
platform_device_register_resndata(&platform_bus, "sh-sci", index, \
scif##index##_resources, \
ARRAY_SIZE(scif##index##_resources), \
&scif##index##_platform_data, \
sizeof(scif##index##_platform_data))
static const struct sh_timer_config cmt00_platform_data __initconst = {
.name = "CMT00",
.timer_bit = 0,
@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = {
&irqc##idx##_data, \
sizeof(struct renesas_irqc_config))
static const struct resource thermal_resources[] __initconst = {
DEFINE_RES_MEM(0xe61f0000, 0x14),
DEFINE_RES_MEM(0xe61f0100, 0x38),
DEFINE_RES_IRQ(gic_spi(69)),
};
#define r8a7791_register_thermal() \
platform_device_register_simple("rcar_thermal", -1, \
thermal_resources, \
ARRAY_SIZE(thermal_resources))
void __init r8a7791_add_dt_devices(void)
{
r8a7791_register_scif(SCIFA0);
r8a7791_register_scif(SCIFA1);
r8a7791_register_scif(SCIFB0);
r8a7791_register_scif(SCIFB1);
r8a7791_register_scif(SCIFB2);
r8a7791_register_scif(SCIFA2);
r8a7791_register_scif(SCIF0);
r8a7791_register_scif(SCIF1);
r8a7791_register_scif(SCIF2);
r8a7791_register_scif(SCIF3);
r8a7791_register_scif(SCIF4);
r8a7791_register_scif(SCIF5);
r8a7791_register_scif(SCIFA3);
r8a7791_register_scif(SCIFA4);
r8a7791_register_scif(SCIFA5);
r8a7791_register_scif(0);
r8a7791_register_scif(1);
r8a7791_register_scif(2);
r8a7791_register_scif(3);
r8a7791_register_scif(4);
r8a7791_register_scif(5);
r8a7791_register_scif(6);
r8a7791_register_scif(7);
r8a7791_register_scif(8);
r8a7791_register_scif(9);
r8a7791_register_scif(10);
r8a7791_register_scif(11);
r8a7791_register_scif(12);
r8a7791_register_scif(13);
r8a7791_register_scif(14);
r8a7791_register_cmt(00);
}
@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void)
{
r8a7791_add_dt_devices();
r8a7791_register_irqc(0);
r8a7791_register_thermal();
}
void __init r8a7791_init_early(void)

29
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/clk/shmobile.h>
#include <linux/clocksource.h>
#include <linux/io.h>
#include <linux/kernel.h>
@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
void __init rcar_gen2_timer_init(void)
{
#ifdef CONFIG_ARM_ARCH_TIMER
#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
u32 mode = rcar_gen2_read_mode_pins();
#endif
#ifdef CONFIG_ARM_ARCH_TIMER
void __iomem *base;
int extal_mhz = 0;
u32 freq;
@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
/* Remap "armgcnt address map" space */
base = ioremap(0xe6080000, PAGE_SIZE);
/* Update registers with correct frequency */
iowrite32(freq, base + CNTFID0);
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
/*
* Update the timer if it is either not running, or is not at the
* right frequency. The timer is only configurable in secure mode
* so this avoids an abort if the loader started the timer and
* entered the kernel in non-secure mode.
*/
if ((ioread32(base + CNTCR) & 1) == 0 ||
ioread32(base + CNTFID0) != freq) {
/* Update registers with correct frequency */
iowrite32(freq, base + CNTFID0);
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
/* make sure arch timer is started by setting bit 0 of CNTCR */
iowrite32(1, base + CNTCR);
}
/* make sure arch timer is started by setting bit 0 of CNTCR */
iowrite32(1, base + CNTCR);
iounmap(base);
#endif /* CONFIG_ARM_ARCH_TIMER */
#ifdef CONFIG_COMMON_CLK
rcar_gen2_clocks_init(mode);
#endif
clocksource_of_init();
}

160
arch/arm/mach-shmobile/setup-sh7372.c
View File

@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
platform_device_register(&sh7372_pfc_device);
}
/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
evt2irq(0x0c00), evt2irq(0x0c00) },
};
/* SCIF */
#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
evt2irq(0x0c20), evt2irq(0x0c20) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
evt2irq(0x0c40), evt2irq(0x0c40) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
evt2irq(0x0c60), evt2irq(0x0c60) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
evt2irq(0x0d20), evt2irq(0x0d20) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
evt2irq(0x0d40), evt2irq(0x0d40) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
/* SCIFB */
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
evt2irq(0x0d60), evt2irq(0x0d60) },
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
/* CMT */
static struct sh_timer_config cmt2_platform_data = {

191
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
ARRAY_SIZE(pfc_resources));
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xe6c40000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(72), gic_spi(72),
gic_spi(72), gic_spi(72) },
};
/* SCIF */
#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xe6c50000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(73), gic_spi(73),
gic_spi(73), gic_spi(73) },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xe6c60000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(74), gic_spi(74),
gic_spi(74), gic_spi(74) },
};
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = 2,
.dev = {
.platform_data = &scif2_platform_data,
},
};
static struct plat_sci_port scif3_platform_data = {
.mapbase = 0xe6c70000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(75), gic_spi(75),
gic_spi(75), gic_spi(75) },
};
static struct platform_device scif3_device = {
.name = "sh-sci",
.id = 3,
.dev = {
.platform_data = &scif3_platform_data,
},
};
static struct plat_sci_port scif4_platform_data = {
.mapbase = 0xe6c80000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(78), gic_spi(78),
gic_spi(78), gic_spi(78) },
};
static struct platform_device scif4_device = {
.name = "sh-sci",
.id = 4,
.dev = {
.platform_data = &scif4_platform_data,
},
};
static struct plat_sci_port scif5_platform_data = {
.mapbase = 0xe6cb0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(79), gic_spi(79),
gic_spi(79), gic_spi(79) },
};
static struct platform_device scif5_device = {
.name = "sh-sci",
.id = 5,
.dev = {
.platform_data = &scif5_platform_data,
},
};
static struct plat_sci_port scif6_platform_data = {
.mapbase = 0xe6cc0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(156), gic_spi(156),
gic_spi(156), gic_spi(156) },
};
static struct platform_device scif6_device = {
.name = "sh-sci",
.id = 6,
.dev = {
.platform_data = &scif6_platform_data,
},
};
static struct plat_sci_port scif7_platform_data = {
.mapbase = 0xe6cd0000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFA,
.irqs = { gic_spi(143), gic_spi(143),
gic_spi(143), gic_spi(143) },
};
static struct platform_device scif7_device = {
.name = "sh-sci",
.id = 7,
.dev = {
.platform_data = &scif7_platform_data,
},
};
static struct plat_sci_port scif8_platform_data = {
.mapbase = 0xe6c30000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIFB,
.irqs = { gic_spi(80), gic_spi(80),
gic_spi(80), gic_spi(80) },
};
static struct platform_device scif8_device = {
.name = "sh-sci",
.id = 8,
.dev = {
.platform_data = &scif8_platform_data,
},
};
SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
static struct sh_timer_config cmt10_platform_data = {
.name = "CMT10",

2
drivers/Makefile
View File

@ -118,7 +118,7 @@ obj-$(CONFIG_SGI_SN) += sn/
obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
obj-$(CONFIG_ARCH_SHMOBILE) += sh/
obj-$(CONFIG_ARCH_SHMOBILE_LEGACY) += sh/
ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
obj-y += clocksource/
endif

187
drivers/tty/serial/sh-sci.c
View File

@ -39,6 +39,7 @@
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/scatterlist.h>
@ -58,6 +59,23 @@
#include "sh-sci.h"
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
#define SCIx_IRQ_IS_MUXED(port) \
((port)->irqs[SCIx_ERI_IRQ] == \
(port)->irqs[SCIx_RXI_IRQ]) || \
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
struct sci_port {
struct uart_port port;
@ -1757,17 +1775,6 @@ static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
if (s->sampling_rate)
return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
switch (s->cfg->scbrr_algo_id) {
case SCBRR_ALGO_1:
return freq / (16 * bps);
case SCBRR_ALGO_2:
return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
case SCBRR_ALGO_3:
return freq / (8 * bps);
case SCBRR_ALGO_4:
return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
}
/* Warn, but use a safe default */
WARN_ON(1);
@ -2105,36 +2112,27 @@ static int sci_init_single(struct platform_device *dev,
port->iotype = UPIO_MEM;
port->line = index;
if (dev->num_resources) {
/* Device has resources, use them. */
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (res == NULL)
return -ENOMEM;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (res == NULL)
return -ENOMEM;
port->mapbase = res->start;
port->mapbase = res->start;
for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
sci_port->irqs[i] = platform_get_irq(dev, i);
for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
sci_port->irqs[i] = platform_get_irq(dev, i);
/* The SCI generates several interrupts. They can be muxed
* together or connected to different interrupt lines. In the
* muxed case only one interrupt resource is specified. In the
* non-muxed case three or four interrupt resources are
* specified, as the BRI interrupt is optional.
*/
if (sci_port->irqs[0] < 0)
return -ENXIO;
/* The SCI generates several interrupts. They can be muxed together or
* connected to different interrupt lines. In the muxed case only one
* interrupt resource is specified. In the non-muxed case three or four
* interrupt resources are specified, as the BRI interrupt is optional.
*/
if (sci_port->irqs[0] < 0)
return -ENXIO;
if (sci_port->irqs[1] < 0) {
sci_port->irqs[1] = sci_port->irqs[0];
sci_port->irqs[2] = sci_port->irqs[0];
sci_port->irqs[3] = sci_port->irqs[0];
}
} else {
/* No resources, use old-style platform data. */
port->mapbase = p->mapbase;
for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
if (sci_port->irqs[1] < 0) {
sci_port->irqs[1] = sci_port->irqs[0];
sci_port->irqs[2] = sci_port->irqs[0];
sci_port->irqs[3] = sci_port->irqs[0];
}
if (p->regtype == SCIx_PROBE_REGTYPE) {
@ -2176,17 +2174,12 @@ static int sci_init_single(struct platform_device *dev,
break;
}
/* Set the sampling rate if the baud rate calculation algorithm isn't
* specified.
/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
* match the SoC datasheet, this should be investigated. Let platform
* data override the sampling rate for now.
*/
if (p->scbrr_algo_id == SCBRR_ALGO_NONE) {
/* SCIFA on sh7723 and sh7724 need a custom sampling rate that
* doesn't match the SoC datasheet, this should be investigated.
* Let platform data override the sampling rate for now.
*/
sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
: sampling_rate;
}
sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
: sampling_rate;
if (!early) {
sci_port->iclk = clk_get(&dev->dev, "sci_ick");
@ -2423,6 +2416,83 @@ static int sci_remove(struct platform_device *dev)
return 0;
}
struct sci_port_info {
unsigned int type;
unsigned int regtype;
};
static const struct of_device_id of_sci_match[] = {
{
.compatible = "renesas,scif",
.data = (void *)&(const struct sci_port_info) {
.type = PORT_SCIF,
.regtype = SCIx_SH4_SCIF_REGTYPE,
},
}, {
.compatible = "renesas,scifa",
.data = (void *)&(const struct sci_port_info) {
.type = PORT_SCIFA,
.regtype = SCIx_SCIFA_REGTYPE,
},
}, {
.compatible = "renesas,scifb",
.data = (void *)&(const struct sci_port_info) {
.type = PORT_SCIFB,
.regtype = SCIx_SCIFB_REGTYPE,
},
}, {
.compatible = "renesas,hscif",
.data = (void *)&(const struct sci_port_info) {
.type = PORT_HSCIF,
.regtype = SCIx_HSCIF_REGTYPE,
},
}, {
/* Terminator */
},
};
MODULE_DEVICE_TABLE(of, of_sci_match);
static struct plat_sci_port *
sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
const struct sci_port_info *info;
struct plat_sci_port *p;
int id;
if (!IS_ENABLED(CONFIG_OF) || !np)
return NULL;
match = of_match_node(of_sci_match, pdev->dev.of_node);
if (!match)
return NULL;
info = match->data;
p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
if (!p) {
dev_err(&pdev->dev, "failed to allocate DT config data\n");
return NULL;
}
/* Get the line number for the aliases node. */
id = of_alias_get_id(np, "serial");
if (id < 0) {
dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
return NULL;
}
*dev_id = id;
p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
p->type = info->type;
p->regtype = info->regtype;
p->scscr = SCSCR_RE | SCSCR_TE;
return p;
}
static int sci_probe_single(struct platform_device *dev,
unsigned int index,
struct plat_sci_port *p,
@ -2455,8 +2525,9 @@ static int sci_probe_single(struct platform_device *dev,
static int sci_probe(struct platform_device *dev)
{
struct plat_sci_port *p = dev_get_platdata(&dev->dev);
struct sci_port *sp = &sci_ports[dev->id];
struct plat_sci_port *p;
struct sci_port *sp;
unsigned int dev_id;
int ret;
/*
@ -2467,9 +2538,24 @@ static int sci_probe(struct platform_device *dev)
if (is_early_platform_device(dev))
return sci_probe_earlyprintk(dev);
if (dev->dev.of_node) {
p = sci_parse_dt(dev, &dev_id);
if (p == NULL)
return -EINVAL;
} else {
p = dev->dev.platform_data;
if (p == NULL) {
dev_err(&dev->dev, "no platform data supplied\n");
return -EINVAL;
}
dev_id = dev->id;
}
sp = &sci_ports[dev_id];
platform_set_drvdata(dev, sp);
ret = sci_probe_single(dev, dev->id, p, sp);
ret = sci_probe_single(dev, dev_id, p, sp);
if (ret)
return ret;
@ -2521,6 +2607,7 @@ static struct platform_driver sci_driver = {
.name = "sh-sci",
.owner = THIS_MODULE,
.pm = &sci_dev_pm_ops,
.of_match_table = of_match_ptr(of_sci_match),
},
};

100
include/dt-bindings/clock/r8a7790-clock.h Normal file
View File

@ -0,0 +1,100 @@
/*
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
#define __DT_BINDINGS_CLOCK_R8A7790_H__
/* CPG */
#define R8A7790_CLK_MAIN 0
#define R8A7790_CLK_PLL0 1
#define R8A7790_CLK_PLL1 2
#define R8A7790_CLK_PLL3 3
#define R8A7790_CLK_LB 4
#define R8A7790_CLK_QSPI 5
#define R8A7790_CLK_SDH 6
#define R8A7790_CLK_SD0 7
#define R8A7790_CLK_SD1 8
#define R8A7790_CLK_Z 9
/* MSTP1 */
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
#define R8A7790_CLK_CMT0 24
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_RT 30
#define R8A7790_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2
#define R8A7790_CLK_SCIFA1 3
#define R8A7790_CLK_SCIFA0 4
#define R8A7790_CLK_SCIFB0 6
#define R8A7790_CLK_SCIFB1 7
#define R8A7790_CLK_SCIFB2 16
#define R8A7790_CLK_SYS_DMAC0 18
#define R8A7790_CLK_SYS_DMAC1 19
/* MSTP3 */
#define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SDHI3 11
#define R8A7790_CLK_SDHI2 12
#define R8A7790_CLK_SDHI1 13
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
#define R8A7790_CLK_USBDMAC0 30
#define R8A7790_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7790_CLK_THERMAL 22
#define R8A7790_CLK_PWM 23
/* MSTP7 */
#define R8A7790_CLK_EHCI 3
#define R8A7790_CLK_HSUSB 4
#define R8A7790_CLK_HSCIF1 16
#define R8A7790_CLK_HSCIF0 17
#define R8A7790_CLK_SCIF1 20
#define R8A7790_CLK_SCIF0 21
#define R8A7790_CLK_DU2 22
#define R8A7790_CLK_DU1 23
#define R8A7790_CLK_DU0 24
#define R8A7790_CLK_LVDS1 25
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
/* MSTP9 */
#define R8A7790_CLK_GPIO5 7
#define R8A7790_CLK_GPIO4 8
#define R8A7790_CLK_GPIO3 9
#define R8A7790_CLK_GPIO2 10
#define R8A7790_CLK_GPIO1 11
#define R8A7790_CLK_GPIO0 12
#define R8A7790_CLK_RCAN1 15
#define R8A7790_CLK_RCAN0 16
#define R8A7790_CLK_IICDVFS 26
#define R8A7790_CLK_I2C3 28
#define R8A7790_CLK_I2C2 29
#define R8A7790_CLK_I2C1 30
#define R8A7790_CLK_I2C0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */

105
include/dt-bindings/clock/r8a7791-clock.h Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
#define __DT_BINDINGS_CLOCK_R8A7791_H__
/* CPG */
#define R8A7791_CLK_MAIN 0
#define R8A7791_CLK_PLL0 1
#define R8A7791_CLK_PLL1 2
#define R8A7791_CLK_PLL3 3
#define R8A7791_CLK_LB 4
#define R8A7791_CLK_QSPI 5
#define R8A7791_CLK_SDH 6
#define R8A7791_CLK_SD0 7
#define R8A7791_CLK_Z 8
/* MSTP1 */
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
#define R8A7791_CLK_CMT0 24
#define R8A7791_CLK_TMU0 25
#define R8A7791_CLK_VSP1_DU1 27
#define R8A7791_CLK_VSP1_DU0 28
#define R8A7791_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7791_CLK_SCIFA2 2
#define R8A7791_CLK_SCIFA1 3
#define R8A7791_CLK_SCIFA0 4
#define R8A7791_CLK_SCIFB0 6
#define R8A7791_CLK_SCIFB1 7
#define R8A7791_CLK_SCIFB2 16
#define R8A7791_CLK_DMAC 18
/* MSTP3 */
#define R8A7791_CLK_TPU0 4
#define R8A7791_CLK_SDHI2 11
#define R8A7791_CLK_SDHI1 12
#define R8A7791_CLK_SDHI0 14
#define R8A7791_CLK_MMCIF0 15
#define R8A7791_CLK_SSUSB 28
#define R8A7791_CLK_CMT1 29
#define R8A7791_CLK_USBDMAC0 30
#define R8A7791_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7791_CLK_THERMAL 22
#define R8A7791_CLK_PWM 23
/* MSTP7 */
#define R8A7791_CLK_HSUSB 4
#define R8A7791_CLK_HSCIF2 13
#define R8A7791_CLK_SCIF5 14
#define R8A7791_CLK_SCIF4 15
#define R8A7791_CLK_HSCIF1 16
#define R8A7791_CLK_HSCIF0 17
#define R8A7791_CLK_SCIF3 18
#define R8A7791_CLK_SCIF2 19
#define R8A7791_CLK_SCIF1 20
#define R8A7791_CLK_SCIF0 21
#define R8A7791_CLK_DU1 23
#define R8A7791_CLK_DU0 24
#define R8A7791_CLK_LVDS0 26
/* MSTP8 */
#define R8A7791_CLK_VIN2 9
#define R8A7791_CLK_VIN1 10
#define R8A7791_CLK_VIN0 11
#define R8A7791_CLK_ETHER 13
#define R8A7791_CLK_SATA1 14
#define R8A7791_CLK_SATA0 15
/* MSTP9 */
#define R8A7791_CLK_GPIO7 4
#define R8A7791_CLK_GPIO6 5
#define R8A7791_CLK_GPIO5 7
#define R8A7791_CLK_GPIO4 8
#define R8A7791_CLK_GPIO3 9
#define R8A7791_CLK_GPIO2 10
#define R8A7791_CLK_GPIO1 11
#define R8A7791_CLK_GPIO0 12
#define R8A7791_CLK_RCAN1 15
#define R8A7791_CLK_RCAN0 16
#define R8A7791_CLK_I2C5 25
#define R8A7791_CLK_IICDVFS 26
#define R8A7791_CLK_I2C4 27
#define R8A7791_CLK_I2C3 28
#define R8A7791_CLK_I2C2 29
#define R8A7791_CLK_I2C1 30
#define R8A7791_CLK_I2C0 31
/* MSTP11 */
#define R8A7791_CLK_SCIFA3 6
#define R8A7791_CLK_SCIFA4 7
#define R8A7791_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */

36
include/linux/serial_sci.h
View File

@ -10,15 +10,6 @@
#define SCIx_NOT_SUPPORTED (-1)
enum {
SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
SCBRR_ALGO_1, /* clk / (16 * bps) */
SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
SCBRR_ALGO_3, /* clk / (8 * bps) */
SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
};
#define SCSCR_TIE (1 << 7)
#define SCSCR_RIE (1 << 6)
#define SCSCR_TE (1 << 5)
@ -59,17 +50,6 @@ enum {
/* HSSRR HSCIF */
#define HSCIF_SRE 0x8000
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
enum {
SCIx_PROBE_REGTYPE,
@ -88,19 +68,6 @@ enum {
SCIx_NR_REGTYPES,
};
#define SCIx_IRQ_MUXED(irq) \
{ \
[SCIx_ERI_IRQ] = (irq), \
[SCIx_RXI_IRQ] = (irq), \
[SCIx_TXI_IRQ] = (irq), \
[SCIx_BRI_IRQ] = (irq), \
}
#define SCIx_IRQ_IS_MUXED(port) \
((port)->irqs[SCIx_ERI_IRQ] == \
(port)->irqs[SCIx_RXI_IRQ]) || \
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
/*
* SCI register subset common for all port types.
* Not all registers will exist on all parts.
@ -129,14 +96,11 @@ struct plat_sci_port_ops {
* Platform device specific platform_data struct
*/
struct plat_sci_port {
unsigned long mapbase; /* resource base */
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
upf_t flags; /* UPF_* flags */
unsigned long capabilities; /* Port features/capabilities */
unsigned int sampling_rate;
unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */
/*