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clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C

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Add clock, reset and power domain support for the I2C channels available
on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2024-06-25 15:13:47 +03:00 committed by Geert Uytterhoeven
parent 1f5ed3ae02
commit c7e58843d1
1 changed files with 20 additions and 0 deletions
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20
drivers/clk/renesas/r9a08g045-cpg.c
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@ -213,6 +213,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
@ -228,6 +232,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
@ -275,6 +283,18 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
DEF_PD("eth1", R9A08G045_PD_ETHER1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
RZG2L_PD_F_NONE),
DEF_PD("i2c0", R9A08G045_PD_I2C0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
RZG2L_PD_F_NONE),
DEF_PD("i2c1", R9A08G045_PD_I2C1,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
RZG2L_PD_F_NONE),
DEF_PD("i2c2", R9A08G045_PD_I2C2,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
RZG2L_PD_F_NONE),
DEF_PD("i2c3", R9A08G045_PD_I2C3,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
RZG2L_PD_F_NONE),
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),