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arm64: mm: Implement 4 levels of translation tables
This patch implements 4 levels of translation tables since 3 levels of page tables with 4KB pages cannot support 40-bit physical address space described in [1] due to the following issue. It is a restriction that kernel logical memory map with 4KB + 3 levels (0xffffffc000000000-0xffffffffffffffff) cannot cover RAM region from 544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create mapping for this region in map_mem function since __phys_to_virt for this region reaches to address overflow. If SoC design follows the document, [1], over 32GB RAM would be placed from 544GB. Even 64GB system is supposed to use the region from 544GB to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels of page tables to avoid hacking __virt_to_phys and __phys_to_virt. However, it is recommended 4 levels of page table should be only enabled if memory map is too sparse or there is about 512GB RAM. References ---------- [1]: Principles of ARM Memory Maps, White Paper, Issue C Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Steve Capper <steve.capper@linaro.org> [catalin.marinas@arm.com: MEMBLOCK_INITIAL_LIMIT removed, same as PUD_SIZE] [catalin.marinas@arm.com: early_ioremap_init() updated for 4 levels] [catalin.marinas@arm.com: 48-bit VA depends on BROKEN until KVM is fixed] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
This commit is contained in:
Jungseok Lee
Catalin Marinas
parent
57e0139041
commit
c79b954bf6
@ -195,12 +195,17 @@ config ARM64_VA_BITS_42
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bool "42-bit"
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depends on ARM64_64K_PAGES
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config ARM64_VA_BITS_48
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bool "48-bit"
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depends on BROKEN
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endchoice
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config ARM64_VA_BITS
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int
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default 39 if ARM64_VA_BITS_39
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default 42 if ARM64_VA_BITS_42
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default 48 if ARM64_VA_BITS_48
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config ARM64_2_LEVELS
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def_bool y if ARM64_64K_PAGES && ARM64_VA_BITS_42
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@ -208,6 +213,9 @@ config ARM64_2_LEVELS
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config ARM64_3_LEVELS
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def_bool y if ARM64_4K_PAGES && ARM64_VA_BITS_39
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config ARM64_4_LEVELS
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def_bool y if ARM64_4K_PAGES && ARM64_VA_BITS_48
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config CPU_BIG_ENDIAN
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bool "Build big-endian kernel"
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help
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@ -33,19 +33,26 @@
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/*
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* The idmap and swapper page tables need some space reserved in the kernel
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* image. Both require a pgd and a next level table to (section) map the
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* kernel. The the swapper also maps the FDT (see __create_page_tables for
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* image. Both require pgd, pud (4 levels only) and pmd tables to (section)
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* map the kernel. The swapper also maps the FDT (see __create_page_tables for
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* more information).
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*/
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#ifdef CONFIG_ARM64_4_LEVELS
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#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (3 * PAGE_SIZE)
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#else
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#define SWAPPER_DIR_SIZE (2 * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
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#endif
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ARM64_2_LEVELS
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#include <asm/pgtable-2level-types.h>
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#else
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#elif defined(CONFIG_ARM64_3_LEVELS)
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#include <asm/pgtable-3level-types.h>
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#else
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#include <asm/pgtable-4level-types.h>
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#endif
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extern void __cpu_clear_user_page(void *p, unsigned long user);
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@ -46,6 +46,26 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
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#endif /* CONFIG_ARM64_2_LEVELS */
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#ifdef CONFIG_ARM64_4_LEVELS
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static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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return (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
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}
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static inline void pud_free(struct mm_struct *mm, pud_t *pud)
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{
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BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
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free_page((unsigned long)pud);
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}
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static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
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{
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set_pgd(pgd, __pgd(__pa(pud) | PUD_TYPE_TABLE));
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}
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#endif /* CONFIG_ARM64_4_LEVELS */
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
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@ -18,8 +18,10 @@
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#ifdef CONFIG_ARM64_2_LEVELS
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#include <asm/pgtable-2level-hwdef.h>
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#else
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#elif defined(CONFIG_ARM64_3_LEVELS)
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#include <asm/pgtable-3level-hwdef.h>
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#else
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#include <asm/pgtable-4level-hwdef.h>
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#endif
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/*
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@ -27,7 +29,7 @@
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*
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* Level 1 descriptor (PUD).
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*/
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#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
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#define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1)
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#define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0)
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#define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0)
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@ -35,7 +35,11 @@
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* VMALLOC and SPARSEMEM_VMEMMAP ranges.
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*/
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#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
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#ifndef CONFIG_ARM64_4_LEVELS
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#define VMALLOC_END (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
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#else
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#define VMALLOC_END (PAGE_OFFSET - UL(0x40000000000) - SZ_64K)
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#endif
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#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
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@ -44,12 +48,16 @@
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#ifndef __ASSEMBLY__
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extern void __pte_error(const char *file, int line, unsigned long val);
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extern void __pmd_error(const char *file, int line, unsigned long val);
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extern void __pud_error(const char *file, int line, unsigned long val);
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extern void __pgd_error(const char *file, int line, unsigned long val);
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#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
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#ifndef CONFIG_ARM64_2_LEVELS
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#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
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#endif
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#ifdef CONFIG_ARM64_4_LEVELS
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#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
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#endif
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#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
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#ifdef CONFIG_SMP
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@ -347,6 +355,30 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
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#endif /* CONFIG_ARM64_2_LEVELS */
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#ifdef CONFIG_ARM64_4_LEVELS
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#define pgd_none(pgd) (!pgd_val(pgd))
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#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
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#define pgd_present(pgd) (pgd_val(pgd))
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static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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*pgdp = pgd;
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dsb(ishst);
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}
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static inline void pgd_clear(pgd_t *pgdp)
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{
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set_pgd(pgdp, __pgd(0));
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}
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static inline pud_t *pgd_page_vaddr(pgd_t pgd)
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{
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return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
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}
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#endif /* CONFIG_ARM64_4_LEVELS */
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/* to find an entry in a page-table-directory */
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#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
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@ -355,6 +387,14 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
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#ifdef CONFIG_ARM64_4_LEVELS
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#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
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static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
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{
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return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
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}
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#endif
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/* Find an entry in the second-level page table.. */
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#ifndef CONFIG_ARM64_2_LEVELS
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#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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@ -100,6 +100,15 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
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}
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#endif
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#ifdef CONFIG_ARM64_4_LEVELS
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static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
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unsigned long addr)
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{
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tlb_add_flush(tlb, addr);
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tlb_remove_page(tlb, virt_to_page(pudp));
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}
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#endif
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static inline void __tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp,
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unsigned long address)
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{
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@ -476,16 +476,42 @@ ENDPROC(__calc_phys_offset)
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.quad PAGE_OFFSET
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/*
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* Macro to populate the PGD for the corresponding block entry in the next
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* level (tbl) for the given virtual address.
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* Macro to populate the PUD for the corresponding block entry in the next
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* level (tbl) for the given virtual address in case of 4 levels.
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*
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* Preserves: pgd, tbl, virt
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* Corrupts: tmp1, tmp2
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* Preserves: pgd, virt
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* Corrupts: tbl, tmp1, tmp2
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* Returns: pud
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*/
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.macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
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.macro create_pud_entry, pgd, tbl, virt, pud, tmp1, tmp2
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#ifdef CONFIG_ARM64_4_LEVELS
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add \tbl, \tbl, #PAGE_SIZE // bump tbl 1 page up.
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// to make room for pud
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add \pud, \pgd, #PAGE_SIZE // pgd points to pud which
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// follows pgd
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lsr \tmp1, \virt, #PUD_SHIFT
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and \tmp1, \tmp1, #PTRS_PER_PUD - 1 // PUD index
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orr \tmp2, \tbl, #3 // PUD entry table type
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str \tmp2, [\pud, \tmp1, lsl #3]
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#else
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mov \pud, \tbl
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#endif
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.endm
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/*
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* Macro to populate the PGD (and possibily PUD) for the corresponding
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* block entry in the next level (tbl) for the given virtual address.
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*
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* Preserves: pgd, virt
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* Corrupts: tmp1, tmp2, tmp3
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* Returns: tbl -> page where block mappings can be placed
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* (changed to make room for pud with 4 levels, preserved otherwise)
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*/
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.macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2, tmp3
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create_pud_entry \pgd, \tbl, \virt, \tmp3, \tmp1, \tmp2
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lsr \tmp1, \virt, #PGDIR_SHIFT
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and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
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orr \tmp2, \tbl, #3 // PGD entry table type
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orr \tmp2, \tmp3, #3 // PGD entry table type
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str \tmp2, [\pgd, \tmp1, lsl #3]
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.endm
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@ -550,7 +576,7 @@ __create_page_tables:
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add x0, x25, #PAGE_SIZE // section table address
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ldr x3, =KERNEL_START
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add x3, x3, x28 // __pa(KERNEL_START)
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create_pgd_entry x25, x0, x3, x5, x6
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create_pgd_entry x25, x0, x3, x1, x5, x6
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ldr x6, =KERNEL_END
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mov x5, x3 // __pa(KERNEL_START)
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add x6, x6, x28 // __pa(KERNEL_END)
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@ -561,7 +587,7 @@ __create_page_tables:
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*/
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add x0, x26, #PAGE_SIZE // section table address
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mov x5, #PAGE_OFFSET
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create_pgd_entry x26, x0, x5, x3, x6
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create_pgd_entry x26, x0, x5, x1, x3, x6
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ldr x6, =KERNEL_END
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mov x3, x24 // phys offset
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create_block_map x0, x7, x3, x5, x6
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@ -339,6 +339,11 @@ void __pmd_error(const char *file, int line, unsigned long val)
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pr_crit("%s:%d: bad pmd %016lx.\n", file, line, val);
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}
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void __pud_error(const char *file, int line, unsigned long val)
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{
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pr_crit("%s:%d: bad pud %016lx.\n", file, line, val);
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}
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void __pgd_error(const char *file, int line, unsigned long val)
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{
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pr_crit("%s:%d: bad pgd %016lx.\n", file, line, val);
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@ -62,6 +62,7 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
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break;
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pud = pud_offset(pgd, addr);
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printk(", *pud=%016llx", pud_val(*pud));
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if (pud_none(*pud) || pud_bad(*pud))
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break;
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@ -104,9 +104,12 @@ void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size)
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EXPORT_SYMBOL(ioremap_cache);
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static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
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#ifndef CONFIG_ARM64_64K_PAGES
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#ifndef CONFIG_ARM64_2_LEVELS
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static pte_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss;
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#endif
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#ifdef CONFIG_ARM64_4_LEVELS
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static pte_t bm_pud[PTRS_PER_PUD] __page_aligned_bss;
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#endif
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static inline pud_t * __init early_ioremap_pud(unsigned long addr)
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{
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@ -144,6 +147,7 @@ void __init early_ioremap_init(void)
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unsigned long addr = fix_to_virt(FIX_BTMAP_BEGIN);
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pgd = pgd_offset_k(addr);
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pgd_populate(&init_mm, pgd, bm_pud);
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pud = pud_offset(pgd, addr);
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pud_populate(&init_mm, pud, bm_pmd);
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pmd = pmd_offset(pud, addr);
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@ -32,6 +32,7 @@
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#include <asm/setup.h>
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#include <asm/sizes.h>
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#include <asm/tlb.h>
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#include <asm/memblock.h>
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#include <asm/mmu_context.h>
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#include "mm.h"
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@ -204,9 +205,16 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
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unsigned long end, unsigned long phys,
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int map_io)
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{
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pud_t *pud = pud_offset(pgd, addr);
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pud_t *pud;
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unsigned long next;
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if (pgd_none(*pgd)) {
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pud = early_alloc(PTRS_PER_PUD * sizeof(pud_t));
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pgd_populate(&init_mm, pgd, pud);
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}
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BUG_ON(pgd_bad(*pgd));
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pud = pud_offset(pgd, addr);
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do {
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next = pud_addr_end(addr, end);
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@ -290,10 +298,10 @@ static void __init map_mem(void)
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* memory addressable from the initial direct kernel mapping.
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*
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* The initial direct kernel mapping, located at swapper_pg_dir,
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* gives us PGDIR_SIZE memory starting from PHYS_OFFSET (which must be
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* gives us PUD_SIZE memory starting from PHYS_OFFSET (which must be
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* aligned to 2MB as per Documentation/arm64/booting.txt).
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*/
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limit = PHYS_OFFSET + PGDIR_SIZE;
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limit = PHYS_OFFSET + PUD_SIZE;
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memblock_set_current_limit(limit);
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/* map all the memory banks */
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