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drm/msm/mdp5: Allocate CTL for each display interface
In MDP5, CTL contains information of the whole pipeline whose output goes down to a display interface. In various cases, one interface may require 2 CRTCs, but only one CTL. Some interfaces also require to use certain CTLs. Instead of allocating CTL for each active CRTC, this change is to associate a CTL with each interface. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Hai Li
Rob Clark
parent
129877819c
commit
c71716b17b
@ -21,6 +21,8 @@ struct mdp5_cmd_encoder {
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struct mdp5_interface intf;
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bool enabled;
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uint32_t bsc;
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struct mdp5_ctl *ctl;
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};
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#define to_mdp5_cmd_encoder(x) container_of(x, struct mdp5_cmd_encoder, base)
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@ -210,13 +212,14 @@ static void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
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mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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pingpong_tearcheck_setup(encoder, mode);
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mdp5_crtc_set_intf(encoder->crtc, &mdp5_cmd_enc->intf);
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mdp5_crtc_set_pipeline(encoder->crtc, &mdp5_cmd_enc->intf,
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mdp5_cmd_enc->ctl);
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}
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static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
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struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
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struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
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struct mdp5_interface *intf = &mdp5_cmd_enc->intf;
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if (WARN_ON(!mdp5_cmd_enc->enabled))
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@ -235,7 +238,7 @@ static void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
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static void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_cmd_encoder *mdp5_cmd_enc = to_mdp5_cmd_encoder(encoder);
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struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
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struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
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struct mdp5_interface *intf = &mdp5_cmd_enc->intf;
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if (WARN_ON(mdp5_cmd_enc->enabled))
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@ -300,7 +303,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
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/* initialize command mode encoder */
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struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
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struct mdp5_interface *intf)
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struct mdp5_interface *intf, struct mdp5_ctl *ctl)
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{
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struct drm_encoder *encoder = NULL;
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struct mdp5_cmd_encoder *mdp5_cmd_enc;
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@ -320,6 +323,7 @@ struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
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memcpy(&mdp5_cmd_enc->intf, intf, sizeof(mdp5_cmd_enc->intf));
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encoder = &mdp5_cmd_enc->base;
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mdp5_cmd_enc->ctl = ctl;
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drm_encoder_init(dev, encoder, &mdp5_cmd_encoder_funcs,
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DRM_MODE_ENCODER_DSI);
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@ -160,8 +160,7 @@ static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
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if (mdp5_crtc->ctl && !crtc->state->enable) {
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/* set STAGE_UNUSED for all layers */
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mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, NULL, 0, 0);
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mdp5_ctl_release(mdp5_crtc->ctl);
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mdp5_ctl_blend(mdp5_crtc->ctl, NULL, 0, 0);
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mdp5_crtc->ctl = NULL;
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}
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}
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@ -289,7 +288,7 @@ static void blend_setup(struct drm_crtc *crtc)
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blender(i)), bg_alpha);
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}
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mdp5_ctl_blend(mdp5_crtc->ctl, lm, stage, plane_cnt, ctl_blend_flags);
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mdp5_ctl_blend(mdp5_crtc->ctl, stage, plane_cnt, ctl_blend_flags);
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out:
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spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
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@ -386,13 +385,6 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
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DBG("%s: check", mdp5_crtc->name);
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/* request a free CTL, if none is already allocated for this CRTC */
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if (state->enable && !mdp5_crtc->ctl) {
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mdp5_crtc->ctl = mdp5_ctlm_request(mdp5_kms->ctlm, crtc);
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if (WARN_ON(!mdp5_crtc->ctl))
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return -EINVAL;
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}
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/* verify that there are not too many planes attached to crtc
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* and that we don't have conflicting mixer stages:
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*/
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@ -735,8 +727,8 @@ void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
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complete_flip(crtc, file);
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}
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/* set interface for routing crtc->encoder: */
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void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
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void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
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struct mdp5_interface *intf, struct mdp5_ctl *ctl)
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{
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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struct mdp5_kms *mdp5_kms = get_kms(crtc);
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@ -759,7 +751,8 @@ void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
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mdp_irq_update(&mdp5_kms->base);
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mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
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mdp5_crtc->ctl = ctl;
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mdp5_ctl_set_pipeline(ctl, intf, lm);
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}
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int mdp5_crtc_get_lm(struct drm_crtc *crtc)
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@ -768,12 +761,6 @@ int mdp5_crtc_get_lm(struct drm_crtc *crtc)
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return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
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}
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struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
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{
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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return WARN_ON(!crtc) ? NULL : mdp5_crtc->ctl;
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}
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void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
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{
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struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
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@ -60,8 +60,6 @@ struct mdp5_ctl {
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u32 pending_ctl_trigger;
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bool cursor_on;
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struct drm_crtc *crtc;
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};
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struct mdp5_ctl_manager {
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@ -168,11 +166,21 @@ static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf)
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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}
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int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf)
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl,
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struct mdp5_interface *intf, int lm)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr);
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if (unlikely(WARN_ON(intf->num != ctl->pipeline.intf.num))) {
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dev_err(mdp5_kms->dev->dev,
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"CTL %d is allocated by INTF %d, but used by INTF %d\n",
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ctl->id, ctl->pipeline.intf.num, intf->num);
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return -EINVAL;
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}
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ctl->lm = lm;
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memcpy(&ctl->pipeline.intf, intf, sizeof(*intf));
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ctl->pipeline.start_mask = mdp_ctl_flush_mask_lm(ctl->lm) |
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@ -335,7 +343,7 @@ static u32 mdp_ctl_blend_ext_mask(enum mdp5_pipe pipe,
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}
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}
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u8 *stage, u32 stage_cnt,
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u8 *stage, u32 stage_cnt,
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u32 ctl_blend_op_flags)
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{
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unsigned long flags;
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@ -358,13 +366,13 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u8 *stage, u32 stage_cnt,
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if (ctl->cursor_on)
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blend_cfg |= MDP5_CTL_LAYER_REG_CURSOR_OUT;
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ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, lm), blend_cfg);
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ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, lm), blend_ext_cfg);
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ctl_write(ctl, REG_MDP5_CTL_LAYER_REG(ctl->id, ctl->lm), blend_cfg);
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ctl_write(ctl, REG_MDP5_CTL_LAYER_EXT_REG(ctl->id, ctl->lm), blend_ext_cfg);
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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ctl->pending_ctl_trigger = mdp_ctl_flush_mask_lm(lm);
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ctl->pending_ctl_trigger = mdp_ctl_flush_mask_lm(ctl->lm);
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DBG("lm%d: blend config = 0x%08x. ext_cfg = 0x%08x", lm,
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DBG("lm%d: blend config = 0x%08x. ext_cfg = 0x%08x", ctl->lm,
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blend_cfg, blend_ext_cfg);
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return 0;
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@ -490,38 +498,18 @@ u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
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return ctl_read(ctl, REG_MDP5_CTL_FLUSH(ctl->id));
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}
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void mdp5_ctl_release(struct mdp5_ctl *ctl)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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unsigned long flags;
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if (unlikely(WARN_ON(ctl->id >= MAX_CTL) || !ctl->busy)) {
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dev_err(ctl_mgr->dev->dev, "CTL %d in bad state (%d)",
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ctl->id, ctl->busy);
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return;
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}
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spin_lock_irqsave(&ctl_mgr->pool_lock, flags);
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ctl->busy = false;
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spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
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DBG("CTL %d released", ctl->id);
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}
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int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
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{
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return WARN_ON(!ctl) ? -EINVAL : ctl->id;
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}
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/*
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* mdp5_ctl_request() - CTL dynamic allocation
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*
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* Note: Current implementation considers that we can only have one CRTC per CTL
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* mdp5_ctl_request() - CTL allocation
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*
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* @return first free CTL
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*/
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
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struct drm_crtc *crtc)
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int intf_num)
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{
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struct mdp5_ctl *ctl = NULL;
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unsigned long flags;
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@ -539,9 +527,8 @@ struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
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}
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ctl = &ctl_mgr->ctls[c];
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ctl->lm = mdp5_crtc_get_lm(crtc);
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ctl->crtc = crtc;
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ctl->pipeline.intf.num = intf_num;
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ctl->lm = -1;
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ctl->busy = true;
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ctl->pending_ctl_trigger = 0;
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DBG("CTL %d allocated", ctl->id);
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@ -32,11 +32,12 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
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* mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
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* which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
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*/
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct drm_crtc *crtc);
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
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int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
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struct mdp5_interface;
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int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf);
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
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int lm);
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int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
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@ -53,7 +54,7 @@ int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
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* (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
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*/
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#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT BIT(0)
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u8 *stage, u32 stage_cnt,
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, u8 *stage, u32 stage_cnt,
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u32 ctl_blend_op_flags);
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/**
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@ -71,8 +72,6 @@ u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
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u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
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u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
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void mdp5_ctl_release(struct mdp5_ctl *ctl);
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#endif /* __MDP5_CTL_H__ */
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@ -27,6 +27,8 @@ struct mdp5_encoder {
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spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */
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bool enabled;
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uint32_t bsc;
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struct mdp5_ctl *ctl;
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};
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#define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
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@ -222,14 +224,15 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_crtc_set_intf(encoder->crtc, &mdp5_encoder->intf);
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mdp5_crtc_set_pipeline(encoder->crtc, &mdp5_encoder->intf,
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mdp5_encoder->ctl);
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}
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static void mdp5_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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int lm = mdp5_crtc_get_lm(encoder->crtc);
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struct mdp5_interface *intf = &mdp5_encoder->intf;
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int intfn = mdp5_encoder->intf.num;
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@ -264,7 +267,7 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_crtc_get_ctl(encoder->crtc);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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struct mdp5_interface *intf = &mdp5_encoder->intf;
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int intfn = mdp5_encoder->intf.num;
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unsigned long flags;
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@ -329,7 +332,7 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
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/* initialize encoder */
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struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
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struct mdp5_interface *intf)
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struct mdp5_interface *intf, struct mdp5_ctl *ctl)
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{
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struct drm_encoder *encoder = NULL;
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struct mdp5_encoder *mdp5_encoder;
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@ -345,6 +348,7 @@ struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
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memcpy(&mdp5_encoder->intf, intf, sizeof(mdp5_encoder->intf));
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encoder = &mdp5_encoder->base;
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mdp5_encoder->ctl = ctl;
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spin_lock_init(&mdp5_encoder->intf_lock);
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@ -198,7 +198,7 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms)
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static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
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enum mdp5_intf_type intf_type, int intf_num,
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enum mdp5_intf_mode intf_mode)
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enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl)
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{
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struct drm_device *dev = mdp5_kms->dev;
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struct msm_drm_private *priv = dev->dev_private;
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@ -211,9 +211,9 @@ static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
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if ((intf_type == INTF_DSI) &&
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(intf_mode == MDP5_INTF_DSI_MODE_COMMAND))
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encoder = mdp5_cmd_encoder_init(dev, &intf);
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encoder = mdp5_cmd_encoder_init(dev, &intf, ctl);
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else
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encoder = mdp5_encoder_init(dev, &intf);
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encoder = mdp5_encoder_init(dev, &intf, ctl);
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if (IS_ERR(encoder)) {
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dev_err(dev->dev, "failed to construct encoder\n");
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@ -251,6 +251,8 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
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const struct mdp5_cfg_hw *hw_cfg =
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mdp5_cfg_get_hw_config(mdp5_kms->cfg);
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enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
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struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;
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struct mdp5_ctl *ctl;
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struct drm_encoder *encoder;
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int ret = 0;
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@ -261,8 +263,14 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
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if (!priv->edp)
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break;
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ctl = mdp5_ctlm_request(ctlm, intf_num);
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if (!ctl) {
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ret = -EINVAL;
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break;
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}
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encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num,
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MDP5_INTF_MODE_NONE);
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MDP5_INTF_MODE_NONE, ctl);
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if (IS_ERR(encoder)) {
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ret = PTR_ERR(encoder);
|
||||
break;
|
||||
@ -274,8 +282,14 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
|
||||
if (!priv->hdmi)
|
||||
break;
|
||||
|
||||
ctl = mdp5_ctlm_request(ctlm, intf_num);
|
||||
if (!ctl) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num,
|
||||
MDP5_INTF_MODE_NONE);
|
||||
MDP5_INTF_MODE_NONE, ctl);
|
||||
if (IS_ERR(encoder)) {
|
||||
ret = PTR_ERR(encoder);
|
||||
break;
|
||||
@ -300,14 +314,20 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
|
||||
if (!priv->dsi[dsi_id])
|
||||
break;
|
||||
|
||||
ctl = mdp5_ctlm_request(ctlm, intf_num);
|
||||
if (!ctl) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
|
||||
mode = (i == MSM_DSI_CMD_ENCODER_ID) ?
|
||||
MDP5_INTF_DSI_MODE_COMMAND :
|
||||
MDP5_INTF_DSI_MODE_VIDEO;
|
||||
dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI,
|
||||
intf_num, mode);
|
||||
if (IS_ERR(dsi_encs)) {
|
||||
ret = PTR_ERR(dsi_encs);
|
||||
intf_num, mode, ctl);
|
||||
if (IS_ERR(dsi_encs[i])) {
|
||||
ret = PTR_ERR(dsi_encs[i]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -228,26 +228,26 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
|
||||
uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
|
||||
|
||||
int mdp5_crtc_get_lm(struct drm_crtc *crtc);
|
||||
struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
|
||||
void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
|
||||
void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf);
|
||||
void mdp5_crtc_set_pipeline(struct drm_crtc *crtc,
|
||||
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
|
||||
void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
|
||||
struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
|
||||
struct drm_plane *plane, int id);
|
||||
|
||||
struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
|
||||
struct mdp5_interface *intf);
|
||||
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
|
||||
int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
|
||||
struct drm_encoder *slave_encoder);
|
||||
|
||||
#ifdef CONFIG_DRM_MSM_DSI
|
||||
struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
|
||||
struct mdp5_interface *intf);
|
||||
struct mdp5_interface *intf, struct mdp5_ctl *ctl);
|
||||
int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
|
||||
struct drm_encoder *slave_encoder);
|
||||
#else
|
||||
static inline struct drm_encoder *mdp5_cmd_encoder_init(
|
||||
struct drm_device *dev, struct mdp5_interface *intf)
|
||||
static inline struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
|
||||
struct mdp5_interface *intf, struct mdp5_ctl *ctl)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user