ARM: dts: imx7: Use audio_mclk_post_div instead audio_mclk_root_clk

[ Upstream commit 4cb7df64c7 ]

The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790),
but according to the reference manual, there is no such gate. Moreover,
the consumer driver of the mentioned clock might gate it and leave
the ECSPI2 (the true owner of that gate) hanging. So lets use the
audio_mclk_post_div, which is the parent.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Abel Vesa 2022-01-27 16:10:51 +02:00 committed by Greg Kroah-Hartman
parent 330de92eb1
commit c7129c401f
7 changed files with 12 additions and 12 deletions

View File

@ -40,7 +40,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -293,7 +293,7 @@
compatible = "fsl,sgtl5000";
#sound-dai-cells = <0>;
reg = <0x0a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&reg_module_3v3_avdd>;

View File

@ -264,7 +264,7 @@
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
clock-names = "mclk";
ldoin-supply = <&reg_audio_3v3>;
iov-supply = <&reg_audio_3v3>;

View File

@ -288,7 +288,7 @@
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
clock-names = "mclk";
wlf,shared-lrclk;
};

View File

@ -31,7 +31,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -41,7 +41,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};

View File

@ -31,7 +31,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -41,7 +41,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};

View File

@ -385,14 +385,14 @@
codec: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
clock-names = "mclk";
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
<&clks IMX7D_PLL_AUDIO_POST_DIV>,
<&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
<&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <884736000>, <12288000>;
};

View File

@ -75,7 +75,7 @@
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
};
};
};
@ -232,7 +232,7 @@
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&vgen4_reg>;