korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-11 12:28:41 +08:00
Code Issues Packages Projects Releases Wiki Activity

ARM: 64-bit DT updates

Browse Source 
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
 changes, but also some new platforms that are worth mentioning:
 
  * Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
    Plus (Kevin)
  * Orange Pi PC2 (Allwinner H5)
  * Freescale LS2088A and LS1088A SoCs
  * Expanded support for Nvidia Tegra186 (and Jetson TX2)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZEA5TAAoJEIwa5zzehBx3uPwP/3NBPKvsDQha/x+PPgtSM1cM
 pUEF1fxsLftrt+pUeRgMZqGE2xu5vVUKEQsr7KDdWMS9LMs50Pp9dTvfxr7A4Asm
 WRRMR7Y3gPbr49uf4+JLLmn0hYXTeaoUftVneBj0qU9Flwe3mQDVULiRjPalWYVB
 g0+NwkPE2lrqrudceA2HiVEXqNlVXCIh2mdMaC7Luo0VEsz7nRHT0TOGPaxnXB3M
 NoJ56FPHtv3x9+C56B5CLJ/+Ya8SLgfqVwwoK8FgoqDzEF3nbhf/WCUyph+gHdP3
 D+jMk7t0tvIW8Ne4TGXenoxBznZxgh5ObpLlKBKPCGJkKxpfuq9koH33MmY/WoUN
 7uh3F3HI2sGr7tY/xaN8H7a9A4mHzipj8nqaAsjAJppIpioecGCFVtkY5q0jfxLC
 aAc1o4zoimdPs9q9mu/qhgKNxWkoTYnwvtWHuwqEOggvSb1ulS1SPS24VkKrc4LI
 XMGbA4mQOuFwZyG4FVfvWzbnhsHzDh4cgHaVGra6z5zoX1MUrvieCWEji+Ul1VWa
 lUJ2sTilvSGkwjGcMUSki5p9GcU8dPXwqKiZqDuGx6Ps4aQsw0vz286BnBeVsusG
 qLRH4nkqbF9xCEz9h71mcU6WMu17EsG9zMoCg5K4EZ+RIG3cgWq0dMWW1LqtRn7S
 2YqayY3+UEyMPN146R1V
 =q3Ix
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Olof Johansson:
 "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
  of smaller changes, but also some new platforms that are worth
  mentioning:

   - Rockchip RK3399 platforms for Chromebooks, including Samsung
     Chromebook Plus (Kevin)

   - Orange Pi PC2 (Allwinner H5)

   - Freescale LS2088A and LS1088A SoCs

   - Expanded support for Nvidia Tegra186 (and Jetson TX2)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
  arm64: dts: Add basic DT to support Spreadtrum's SP9860G
  arm64: dts: exynos: Use - instead of @ for DT OPP entries
  arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
  arm64: dts: juno: add information about L1 and L2 caches
  arm64: dts: juno: fix few unit address format warnings
  arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
  arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
  arm64: marvell: dts: add crypto engine description for 7k/8k
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: dts: marvell: add eMMC support for Armada 37xx
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  ...
This commit is contained in:
Linus Torvalds 2017-05-09 10:07:33 -07:00
commit c6778ff813
130 changed files with 11049 additions and 1407 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/arm/amlogic.txt
View File

@ -43,8 +43,11 @@ Board compatible values:
- "wetek,hub" (Meson gxbb)
- "wetek,play2" (Meson gxbb)
- "amlogic,p212" (Meson gxl s905x)
- "khadas,vim" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "hwacom,amazetv" (Meson gxl s905x)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "nexbox,a95x" (Meson gxbb or Meson gxl s905x)

8
Documentation/devicetree/bindings/arm/cavium-thunder2.txt Normal file
View File

@ -0,0 +1,8 @@
Cavium ThunderX2 CN99XX platform tree bindings
----------------------------------------------
Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
These SoC uses the "cavium,thunder2" core which will be compatible
with "brcm,vulcan".

1
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -170,6 +170,7 @@ nodes to be present and contain the properties described below.
"brcm,brahma-b15"
"brcm,vulcan"
"cavium,thunder"
"cavium,thunder2"
"faraday,fa526"
"intel,sa110"
"intel,sa1100"

23
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -179,6 +179,18 @@ LS1046A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
LS1088A SoC
Required root node properties:
- compatible = "fsl,ls1088a";
LS1088A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
LS1088A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
LS2080A SoC
Required root node properties:
- compatible = "fsl,ls2080a";
@ -195,3 +207,14 @@ LS2080A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
LS2088A SoC
Required root node properties:
- compatible = "fsl,ls2088a";
LS2088A ARMv8 based QDS Board
Required root node properties:
- compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
LS2088A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";

8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -4,6 +4,14 @@ Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
Hi3798cv200 Poplar Board
Required root node properties:
- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";

24
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -59,6 +59,17 @@ Rockchip platforms device tree bindings
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
"google,veyron", "rockchip,rk3288";
- Google Gru (dev-board):
Required root node properties:
- compatible = "google,gru-rev15", "google,gru-rev14",
"google,gru-rev13", "google,gru-rev12",
"google,gru-rev11", "google,gru-rev10",
"google,gru-rev9", "google,gru-rev8",
"google,gru-rev7", "google,gru-rev6",
"google,gru-rev5", "google,gru-rev4",
"google,gru-rev3", "google,gru-rev2",
"google,gru", "rockchip,rk3399";
- Google Jaq (Haier Chromebook 11 and more):
Required root node properties:
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
@ -73,6 +84,15 @@ Rockchip platforms device tree bindings
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
- Google Kevin (Samsung Chromebook Plus):
Required root node properties:
- compatible = "google,kevin-rev15", "google,kevin-rev14",
"google,kevin-rev13", "google,kevin-rev12",
"google,kevin-rev11", "google,kevin-rev10",
"google,kevin-rev9", "google,kevin-rev8",
"google,kevin-rev7", "google,kevin-rev6",
"google,kevin", "google,gru", "rockchip,rk3399";
- Google Mickey (Asus Chromebit CS10):
Required root node properties:
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
@ -141,6 +161,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
- Rockchip RK3328 evb:
Required root node properties:
- compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";

3
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
View File

@ -5,7 +5,8 @@ controllers within the SoC.
Required Properties:
- compatible: should be "amlogic,gxbb-clkc"
- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
or "amlogic,gxl-clkc" for GXL and GXM SoC.
- reg: physical base address of the clock controller and length of memory
mapped region.

1
Documentation/devicetree/bindings/clock/qoriq-clock.txt
View File

@ -35,6 +35,7 @@ Required properties:
* "fsl,ls1021a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

1
Documentation/devicetree/bindings/soc/rockchip/grf.txt
View File

@ -18,6 +18,7 @@ Required Properties:
- "rockchip,rk3188-grf", "syscon": for rk3188
- "rockchip,rk3228-grf", "syscon": for rk3228
- "rockchip,rk3288-grf", "syscon": for rk3288
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- compatible: PMUGRF should be one of the following:

2
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -139,6 +139,7 @@ holt Holt Integrated Circuits, Inc.
honeywell Honeywell
hp Hewlett Packard
holtek Holtek Semiconductor, Inc.
hwacom HwaCom Systems Inc.
i2se I2SE GmbH
ibm International Business Machines (IBM)
idt Integrated Device Technologies, Inc.
@ -162,6 +163,7 @@ jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
keithkoep Keith & Koep GmbH
keymile Keymile GmbH
khadas Khadas
kinetic Kinetic Technologies
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation

2
arch/arm/boot/dts/meson8.dtsi
View File

@ -106,6 +106,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_cbus 0 0 120>;
};
spi_nor_pins: nor {
@ -148,6 +149,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 120 16>;
};
uart_ao_a_pins: uart_ao_a {

2
arch/arm/boot/dts/meson8b.dtsi
View File

@ -198,6 +198,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_cbus 0 0 130>;
};
};
@ -215,6 +216,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 130 16>;
};
uart_ao_a_pins: uart_ao_a {

45
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -68,31 +68,12 @@
clock-output-names = "osc32k";
};
apb0: apb0_clk {
compatible = "fixed-factor-clock";
iosc: internal-osc-clk {
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&osc24M>;
clock-output-names = "apb0";
};
apb0_gates: clk@01f01428 {
compatible = "allwinner,sun8i-h3-apb0-gates-clk",
"allwinner,sun4i-a10-gates-clk";
reg = <0x01f01428 0x4>;
#clock-cells = <1>;
clocks = <&apb0>;
clock-indices = <0>, <1>;
clock-output-names = "apb0_pio", "apb0_ir";
};
ir_clk: ir_clk@01f01454 {
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01f01454 0x4>;
#clock-cells = <0>;
clocks = <&osc32k>, <&osc24M>;
clock-output-names = "ir";
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
};
@ -576,9 +557,12 @@
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
apb0_reset: reset@01f014b0 {
reg = <0x01f014b0 0x4>;
compatible = "allwinner,sun6i-a31-clock-reset";
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -589,9 +573,9 @@
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clocks = <&r_ccu 4>, <&r_ccu 11>;
clock-names = "apb", "ir";
resets = <&apb0_reset 1>;
resets = <&r_ccu 0>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01f02000 0x40>;
status = "disabled";
@ -601,9 +585,8 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_reset 0>;
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;

1
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

29
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -98,6 +98,14 @@
clock-output-names = "osc32k";
};
iosc: internal-osc-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
@ -394,5 +402,26 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
r_pio: pinctrl@01f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};

188
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts Normal file
View File

@ -0,0 +1,188 @@
/*
* Copyright (C) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "Xunlong Orange Pi PC 2";
compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr {
label = "orangepi:green:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
status {
label = "orangepi:red:status";
gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
};
};
r-gpio-keys {
compatible = "gpio-keys";
sw4 {
label = "sw4";
linux,code = <BTN_0>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
};
};
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
status = "okay";
};
};
&codec {
allwinner,audio-routing =
"Line Out", "LINEOUT",
"MIC1", "Mic",
"Mic", "MBIAS";
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
/* USB Type-A ports' VBUS is always on */
usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
usb0_vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};

124
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi Normal file
View File

@ -0,0 +1,124 @@
/*
* Copyright (C) 2016 ARM Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sunxi-h3-h5.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&ccu {
compatible = "allwinner,sun50i-h5-ccu";
};
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc";
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
};
&mmc1 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc";
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
};
&mmc2 {
compatible = "allwinner,sun50i-h5-emmc",
"allwinner,sun50i-a64-emmc";
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
};
&pio {
compatible = "allwinner,sun50i-h5-pinctrl";
};

1
arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi Symbolic link
View File

@ -0,0 +1 @@
../../../../arm/boot/dts/sunxi-h3-h5.dtsi

2
arch/arm64/boot/dts/amlogic/Makefile
View File

@ -7,9 +7,11 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb

39
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@ -98,6 +98,27 @@
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
/* This UART is brought out to the DB9 connector */
@ -188,3 +209,21 @@
&ethmac {
status = "okay";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

80
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@ -71,6 +71,14 @@
reg = <0x0 0x10000000 0x0 0x200000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
cpus {
@ -233,7 +241,7 @@
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@ -279,7 +287,7 @@
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@ -288,7 +296,7 @@
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
@ -296,6 +304,14 @@
status = "disabled";
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
watchdog@98d0 {
compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
@ -317,7 +333,7 @@
};
sram: sram@c8000000 {
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
reg = <0x0 0xc8000000 0x0 0x14000>;
#address-cells = <1>;
@ -325,12 +341,12 @@
ranges = <0 0x0 0xc8000000 0x14000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-gxbb-scp-shmem";
compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
reg = <0x13400 0x400>;
};
};
@ -342,6 +358,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
clkc_AO: clock-controller@040 {
compatible = "amlogic,gx-aoclkc", "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
@ -358,6 +381,15 @@
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm_AO_ab: pwm@550 {
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
reg = <0x0 0x00550 0x0 0x10>;
@ -366,7 +398,7 @@
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@ -386,7 +418,6 @@
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
@ -410,7 +441,6 @@
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
phy-mode = "rgmii";
status = "disabled";
};
@ -457,6 +487,38 @@
cvbs_vdac_port: port@0 {
reg = <0>;
};
/* HDMI-TX output port */
hdmi_tx_port: port@1 {
reg = <1>;
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_tx_in>;
};
};
};
hdmi_tx: hdmi-tx@c883a000 {
compatible = "amlogic,meson-gx-dw-hdmi";
reg = <0x0 0xc883a000 0x0 0x1c>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;
hdmi_tx_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
/* TMDS Output */
hdmi_tx_tmds_port: port@1 {
reg = <1>;
};
};
};
};

40
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
View File

@ -152,6 +152,17 @@
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&uart_AO {
@ -164,7 +175,24 @@
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* IC Plus IP101GR (0x02430c54) */
reg = <0>;
};
};
};
&ir {
@ -245,3 +273,15 @@
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

80
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -96,7 +96,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
@ -152,6 +152,13 @@
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
amlogic,tx-delay-ns = <2>;
mdio {
compatible = "snps,dwmac-mdio";
@ -165,6 +172,57 @@
};
};
&pinctrl_aobus {
gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
"USB HUB nRESET", "USB OTG Power En",
"J7 Header Pin2", "IR In", "J7 Header Pin4",
"J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7",
"HDMI CEC", "SYS LED";
};
&pinctrl_periphs {
gpio-line-names = /* Bank GPIOZ */
"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
"Eth PHY nRESET", "Eth PHY Intc",
/* Bank GPIOH */
"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
/* Bank BOOT */
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
"eMMC Reset", "eMMC CMD",
"", "", "", "", "", "", "",
/* Bank CARD */
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
"SDCard D3", "SDCard D2", "SDCard Det",
/* Bank GPIODV */
"", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "",
"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
"PWM D", "PWM B",
/* Bank GPIOY */
"Revision Bit0", "Revision Bit1", "",
"J2 Header Pin35", "", "", "", "J2 Header Pin36",
"J2 Header Pin31", "", "", "", "TF VDD En",
"J2 Header Pin32", "J2 Header Pin26", "", "",
/* Bank GPIOX */
"J2 Header Pin29", "J2 Header Pin24",
"J2 Header Pin23", "J2 Header Pin22",
"J2 Header Pin21", "J2 Header Pin18",
"J2 Header Pin33", "J2 Header Pin19",
"J2 Header Pin16", "J2 Header Pin15",
"J2 Header Pin12", "J2 Header Pin13",
"J2 Header Pin8", "J2 Header Pin10",
"", "", "", "", "",
"J2 Header Pin11", "", "J2 Header Pin7",
/* Bank GPIOCLK */
"", "", "", "",
/* GPIO_TEST_N */
"";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@ -177,6 +235,21 @@
pinctrl-names = "default";
};
&gpio_ao {
/*
* WARNING: The USB Hub on the Odroid-C2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_otg_pwr>;
@ -194,6 +267,11 @@
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc1v8>;
};
/* SD */
&sd_emmc_b {
status = "okay";

25
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
View File

@ -96,6 +96,31 @@
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
};
};
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;

11
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
View File

@ -50,3 +50,14 @@
compatible = "amlogic,p201", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P201 Development Board";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
};

29
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View File

@ -135,6 +135,17 @@
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
/* This UART is brought out to the DB9 connector */
@ -144,12 +155,6 @@
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
@ -250,3 +255,15 @@
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

21
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View File

@ -115,7 +115,6 @@
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
@ -128,6 +127,26 @@
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
};
&usb0_phy {

26
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
View File

@ -64,3 +64,29 @@
status = "disabled";
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
};

26
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
View File

@ -87,6 +87,32 @@
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_rgmii_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
phy-mode = "rgmii";
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
};
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;

172
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -97,17 +97,6 @@
};
};
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
};
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
@ -129,6 +118,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
@ -203,30 +193,62 @@
function = "pwm_ao_b";
};
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
i2s_am_clk_pins: i2s_am_clk {
mux {
groups = "i2s_am_clk";
function = "i2s_out_ao";
};
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
i2s_out_ao_clk_pins: i2s_out_ao_clk {
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out_ao";
};
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2s_out_lr_clk_pins: i2s_out_lr_clk {
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out_ao";
};
};
i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
mux {
groups = "i2s_out_ch01_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
};
};
spdif_out_ao_6_pins: spdif_out_ao_6 {
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
};
};
spdif_out_ao_13_pins: spdif_out_ao_13 {
mux {
groups = "spdif_out_ao_13";
function = "spdif_out_ao";
};
};
};
};
@ -245,6 +267,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 120>;
};
emmc_pins: emmc {
@ -467,6 +490,34 @@
function = "hdmi_i2c";
};
};
i2sout_ch23_y_pins: i2sout_ch23_y {
mux {
groups = "i2sout_ch23_y";
function = "i2s_out";
};
};
i2sout_ch45_y_pins: i2sout_ch45_y {
mux {
groups = "i2sout_ch45_y";
function = "i2s_out";
};
};
i2sout_ch67_y_pins: i2sout_ch67_y {
mux {
groups = "i2sout_ch67_y";
function = "i2s_out";
};
};
spdif_out_y_pins: spdif_out_y {
mux {
groups = "spdif_out_y";
function = "spdif_out";
};
};
};
};
@ -478,10 +529,51 @@
};
};
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
@ -521,6 +613,10 @@
clock-names = "core", "clkin0", "clkin1";
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
@ -529,3 +625,15 @@
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

43
arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright (c) 2017 BayLibre SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
&apb {
mali: gpu@c0000 {
compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
reg = <0x0 0xc0000 0x0 0x40000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp", "gpmmu", "pp", "pmu",
"pp0", "ppmmu0", "pp1", "ppmmu1",
"pp2", "ppmmu2";
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
clock-names = "bus", "core";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
<&clkc CLKID_MALI_0>,
<&clkc CLKID_MALI>; /* Glitch free mux */
assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>;
assigned-clock-rates = <0>, /* Do Nothing */
<666666666>,
<0>; /* Do Nothing */
};
};

42
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
View File

@ -43,12 +43,47 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905d.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905D) P230 Development Board";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1710000>;
button-function {
label = "Update";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <10000>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
/* P230 has exclusive choice between internal or external PHY */
@ -59,6 +94,8 @@
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
/* External PHY reset is shared with internal PHY Led signals */
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
@ -75,3 +112,8 @@
max-speed = <1000>;
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
View File

@ -42,6 +42,7 @@
*/
#include "meson-gxl.dtsi"
#include "meson-gxl-mali.dtsi"
/ {
compatible = "amlogic,s905d", "amlogic,meson-gxl";

164
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts Normal file
View File

@ -0,0 +1,164 @@
/*
* Copyright (c) 2017 Carlo Caione
* Copyright (c) 2016 BayLibre, Inc.
* Author: Neil Armstrong <narmstrong@kernel.org>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
/ {
compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl";
model = "Hwacom AmazeTV (S905X)";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vddio_card: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "VDDIO_CARD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
/* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
states = <1800000 0
3300000 1>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
status = "okay";
phy-mode = "rmii";
phy-handle = <&internal_phy>;
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_card>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

114
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts Normal file
View File

@ -0,0 +1,114 @@
/*
* Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxl-s905x-p212.dtsi"
/ {
compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
model = "Khadas VIM";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1710000>;
button-function {
label = "Function";
linux,code = <KEY_FN>;
press-threshold-microvolt = <10000>;
};
};
aliases {
serial2 = &uart_AO_B;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
};
pwmleds {
compatible = "pwm-leds";
power {
label = "vim:red:power";
pwms = <&pwm_AO_ab 1 7812500 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
};
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;
pinctrl-names = "default";
rtc: rtc@51 {
/* has to be enabled manually when a battery is connected: */
status = "disabled";
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
};
};
&ir {
linux,rc-map-name = "rc-geekbox";
};
&pwm_AO_ab {
status = "okay";
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
&pwm_ef {
pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
};
&sd_emmc_a {
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
&uart_AO {
status = "okay";
};
/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
&uart_AO_B {
status = "okay";
pinctrl-0 = <&uart_ao_b_pins>;
pinctrl-names = "default";
};

23
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
View File

@ -127,6 +127,17 @@
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
&uart_AO {
@ -219,3 +230,15 @@
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

21
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
View File

@ -43,23 +43,26 @@
/dts-v1/;
#include "meson-gxl-s905x.dtsi"
#include "meson-gxl-s905x-p212.dtsi"
/ {
compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
model = "Amlogic Meson GXL (S905X) P212 Development Board";
aliases {
serial0 = &uart_AO;
};
cvbs-connector {
compatible = "composite-video-connector";
chosen {
stdout-path = "serial0:115200n8";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};

173
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi Normal file
View File

@ -0,0 +1,173 @@
/*
* Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
* Based on meson-gx-p23x-q20x.dtsi:
* - Copyright (c) 2016 Endless Computers, Inc.
* Author: Carlo Caione <carlo@endlessm.com>
* - Copyright (c) 2016 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/* Common DTSI for devices which are based on the P212 reference board. */
#include "meson-gxl-s905x.dtsi"
/ {
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
};
&ethmac {
status = "okay";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* Wireless SDIO Module */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
cd-inverted;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&clkc CLKID_FCLK_DIV4>;
clock-names = "clkin0";
};
/* This is connected to the Bluetooth module: */
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
View File

@ -42,6 +42,7 @@
*/
#include "meson-gxl.dtsi"
#include "meson-gxl-mali.dtsi"
/ {
compatible = "amlogic,s905x", "amlogic,meson-gxl";

194
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -44,6 +44,7 @@
#include "meson-gx.dtsi"
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/gpio/meson-gxl-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
/ {
compatible = "amlogic,meson-gxl";
@ -79,6 +80,7 @@
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_aobus 0 0 14>;
};
uart_ao_a_pins: uart_ao_a {
@ -103,6 +105,13 @@
};
};
uart_ao_b_0_1_pins: uart_ao_b_0_1 {
mux {
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
function = "uart_ao_b";
};
};
uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
mux {
groups = "uart_cts_ao_b",
@ -118,12 +127,69 @@
};
};
i2c_ao_pins: i2c_ao {
mux {
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
};
};
pwm_ao_a_3_pins: pwm_ao_a_3 {
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a";
};
};
pwm_ao_a_8_pins: pwm_ao_a_8 {
mux {
groups = "pwm_ao_a_8";
function = "pwm_ao_a";
};
};
pwm_ao_b_pins: pwm_ao_b {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
pwm_ao_b_6_pins: pwm_ao_b_6 {
mux {
groups = "pwm_ao_b_6";
function = "pwm_ao_b";
};
};
i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
mux {
groups = "i2s_out_ch23_ao";
function = "i2s_out_ao";
};
};
i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
mux {
groups = "i2s_out_ch45_ao";
function = "i2s_out_ao";
};
};
spdif_out_ao_6_pins: spdif_out_ao_6 {
mux {
groups = "spdif_out_ao_6";
function = "spdif_out_ao";
};
};
spdif_out_ao_9_pins: spdif_out_ao_9 {
mux {
groups = "spdif_out_ao_9";
function = "spdif_out_ao";
};
};
};
};
@ -142,6 +208,7 @@
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 14 101>;
};
emmc_pins: emmc {
@ -154,6 +221,16 @@
};
};
nor_pins: nor {
mux {
groups = "nor_d",
"nor_q",
"nor_c",
"nor_cs";
function = "nor";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
@ -277,6 +354,34 @@
};
};
pwm_a_pins: pwm_a {
mux {
groups = "pwm_a";
function = "pwm_a";
};
};
pwm_b_pins: pwm_b {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
pwm_c_pins: pwm_c {
mux {
groups = "pwm_c";
function = "pwm_c";
};
};
pwm_d_pins: pwm_d {
mux {
groups = "pwm_d";
function = "pwm_d";
};
};
pwm_e_pins: pwm_e {
mux {
groups = "pwm_e";
@ -284,6 +389,20 @@
};
};
pwm_f_clk_pins: pwm_f_clk {
mux {
groups = "pwm_f_clk";
function = "pwm_f";
};
};
pwm_f_x_pins: pwm_f_x {
mux {
groups = "pwm_f_x";
function = "pwm_f";
};
};
hdmi_hpd_pins: hdmi_hpd {
mux {
groups = "hdmi_hpd";
@ -297,6 +416,61 @@
function = "hdmi_i2c";
};
};
i2s_am_clk_pins: i2s_am_clk {
mux {
groups = "i2s_am_clk";
function = "i2s_out";
};
};
i2s_out_ao_clk_pins: i2s_out_ao_clk {
mux {
groups = "i2s_out_ao_clk";
function = "i2s_out";
};
};
i2s_out_lr_clk_pins: i2s_out_lr_clk {
mux {
groups = "i2s_out_lr_clk";
function = "i2s_out";
};
};
i2s_out_ch01_pins: i2s_out_ch01 {
mux {
groups = "i2s_out_ch01";
function = "i2s_out";
};
};
i2sout_ch23_z_pins: i2sout_ch23_z {
mux {
groups = "i2sout_ch23_z";
function = "i2s_out";
};
};
i2sout_ch45_z_pins: i2sout_ch45_z {
mux {
groups = "i2sout_ch45_z";
function = "i2s_out";
};
};
i2sout_ch67_z_pins: i2sout_ch67_z {
mux {
groups = "i2sout_ch67_z";
function = "i2s_out";
};
};
spdif_out_h_pins: spdif_out_ao_h {
mux {
groups = "spdif_out_h";
function = "spdif_out";
};
};
};
eth-phy-mux {
@ -339,6 +513,10 @@
clocks = <&clkc CLKID_I2C>;
};
&i2c_AO {
clocks = <&clkc CLKID_AO_I2C>;
};
&i2c_B {
clocks = <&clkc CLKID_I2C>;
};
@ -378,6 +556,22 @@
clock-names = "core", "clkin0", "clkin1";
};
&spifc {
clocks = <&clkc CLKID_SPI>;
};
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
};
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_CLK81>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
};

25
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
View File

@ -100,6 +100,17 @@
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
};
/* This UART is brought out to the DB9 connector */
@ -162,6 +173,8 @@
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-active-low;
@ -183,3 +196,15 @@
remote-endpoint = <&cvbs_connector_in>;
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};

42
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
View File

@ -43,12 +43,47 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "meson-gxm.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
model = "Amlogic Meson GXM (S912) Q200 Development Board";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1710000>;
button-function {
label = "Update";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <10000>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
/* Q200 has exclusive choice between internal or external PHY */
@ -59,6 +94,8 @@
/* Select external PHY by default */
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
/* External PHY reset is shared with internal PHY Led signals */
snps,reset-gpio = <&gpio GPIOZ_14 0>;
snps,reset-delays-us = <0 10000 1000000>;
@ -75,3 +112,8 @@
max-speed = <1000>;
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};

3
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
View File

@ -130,3 +130,6 @@
compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
};
&hdmi_tx {
compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
};

4
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -428,7 +428,7 @@
};
};
pcie_ctlr: pcie-controller@40000000 {
pcie_ctlr: pcie@40000000 {
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
device_type = "pci";
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
@ -699,7 +699,7 @@
<0x00000008 0x80000000 0x1 0x80000000>;
};
smb@08000000 {
smb@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;

12
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
View File

@ -137,7 +137,7 @@
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysctl: sysctl@020000 {
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
@ -148,7 +148,7 @@
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
apbregs@010000 {
apbregs@10000 {
compatible = "syscon", "simple-mfd";
reg = <0x010000 0x1000>;
@ -216,7 +216,7 @@
};
};
mmci@050000 {
mmci@50000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <5>;
@ -228,7 +228,7 @@
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
kmi@60000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <8>;
@ -236,7 +236,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
kmi@70000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <8>;
@ -244,7 +244,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
wdt@0f0000 {
wdt@f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x10000>;
interrupts = <7>;

42
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -89,6 +89,12 @@
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -100,6 +106,12 @@
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -111,6 +123,12 @@
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -122,6 +140,12 @@
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -133,6 +157,12 @@
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -144,6 +174,12 @@
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -152,10 +188,16 @@
A57_L2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
A53_L2: l2-cache1 {
compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
};

42
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -89,6 +89,12 @@
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -100,6 +106,12 @@
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -111,6 +123,12 @@
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -122,6 +140,12 @@
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -133,6 +157,12 @@
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -144,6 +174,12 @@
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -152,10 +188,16 @@
A72_L2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
A53_L2: l2-cache1 {
compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
};

42
arch/arm64/boot/dts/arm/juno.dts
View File

@ -88,6 +88,12 @@
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -99,6 +105,12 @@
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -110,6 +122,12 @@
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -121,6 +139,12 @@
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -132,6 +156,12 @@
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -143,6 +173,12 @@
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@ -151,10 +187,16 @@
A57_L2: l2-cache0 {
compatible = "cache";
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
A53_L2: l2-cache1 {
compatible = "cache";
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
};

1
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,6 +1,5 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

38
arch/arm64/boot/dts/broadcom/ns2-svk.dts
View File

@ -57,55 +57,55 @@
};
&enet {
status = "ok";
status = "okay";
};
&pci_phy0 {
status = "ok";
status = "okay";
};
&pci_phy1 {
status = "ok";
status = "okay";
};
&pcie0 {
status = "ok";
status = "okay";
};
&pcie4 {
status = "ok";
status = "okay";
};
&pcie8 {
status = "ok";
status = "okay";
};
&i2c0 {
status = "ok";
status = "okay";
};
&i2c1 {
status = "ok";
status = "okay";
};
&uart0 {
status = "ok";
status = "okay";
};
&uart1 {
status = "ok";
status = "okay";
};
&uart2 {
status = "ok";
status = "okay";
};
&uart3 {
status = "ok";
status = "okay";
};
&ssp0 {
status = "ok";
status = "okay";
slic@0 {
compatible = "silabs,si3226x";
@ -126,7 +126,7 @@
};
&ssp1 {
status = "ok";
status = "okay";
at25@0 {
compatible = "atmel,at25";
@ -150,23 +150,23 @@
};
&sata_phy0 {
status = "ok";
status = "okay";
};
&sata_phy1 {
status = "ok";
status = "okay";
};
&sata {
status = "ok";
status = "okay";
};
&sdio0 {
status = "ok";
status = "okay";
};
&sdio1 {
status = "ok";
status = "okay";
};
&nand {

20
arch/arm64/boot/dts/broadcom/ns2-xmc.dts
View File

@ -54,15 +54,15 @@
};
&enet {
status = "ok";
status = "okay";
};
&i2c0 {
status = "ok";
status = "okay";
};
&i2c1 {
status = "ok";
status = "okay";
};
&mdio_mux_iproc {
@ -122,27 +122,27 @@
};
&pci_phy0 {
status = "ok";
status = "okay";
};
&pcie0 {
status = "ok";
status = "okay";
};
&pcie8 {
status = "ok";
status = "okay";
};
&sata_phy0 {
status = "ok";
status = "okay";
};
&sata_phy1 {
status = "ok";
status = "okay";
};
&sata {
status = "ok";
status = "okay";
};
&qspi {
@ -187,5 +187,5 @@
};
&uart3 {
status = "ok";
status = "okay";
};

24
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -222,6 +222,12 @@
brcm,use-bcm-hdr;
};
crypto0: crypto@612d0000 {
compatible = "brcm,spum-crypto";
reg = <0x612d0000 0x900>;
mboxes = <&pdc0 0>;
};
pdc1: iproc-pdc1@612e0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x612e0000 0x445>; /* PDC FS1 regs */
@ -232,6 +238,12 @@
brcm,use-bcm-hdr;
};
crypto1: crypto@612f0000 {
compatible = "brcm,spum-crypto";
reg = <0x612f0000 0x900>;
mboxes = <&pdc1 0>;
};
pdc2: iproc-pdc2@61300000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x61300000 0x445>; /* PDC FS2 regs */
@ -242,6 +254,12 @@
brcm,use-bcm-hdr;
};
crypto2: crypto@61310000 {
compatible = "brcm,spum-crypto";
reg = <0x61310000 0x900>;
mboxes = <&pdc2 0>;
};
pdc3: iproc-pdc3@61320000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0x61320000 0x445>; /* PDC FS3 regs */
@ -252,6 +270,12 @@
brcm,use-bcm-hdr;
};
crypto3: crypto@61330000 {
compatible = "brcm,spum-crypto";
reg = <0x61330000 0x900>;
mboxes = <&pdc3 0>;
};
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;

1
arch/arm64/boot/dts/cavium/Makefile
View File

@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

9
arch/arm64/boot/dts/broadcom/vulcan-eval.dts → arch/arm64/boot/dts/cavium/thunder2-99xx.dts
View File

@ -1,6 +1,7 @@
/*
* dts file for Broadcom (BRCM) Vulcan Evaluation Platform
* dts file for Cavium ThunderX2 CN99XX Evaluation Platform
*
* Copyright (c) 2017 Cavium Inc.
* Copyright (c) 2013-2016 Broadcom
*
* This program is free software; you can redistribute it and/or
@ -11,11 +12,11 @@
/dts-v1/;
#include "vulcan.dtsi"
#include "thunder2-99xx.dtsi"
/ {
model = "Broadcom Vulcan Eval Platform";
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
model = "Cavium ThunderX2 CN99XX";
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
memory {
device_type = "memory";

15
arch/arm64/boot/dts/broadcom/vulcan.dtsi → arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
View File

@ -1,6 +1,7 @@
/*
* dtsi file for Broadcom (BRCM) Vulcan processor
* dtsi file for Cavium ThunderX2 CN99XX processor
*
* Copyright (c) 2017 Cavium Inc.
* Copyright (c) 2013-2016 Broadcom
* Author: Zi Shen Lim <zlim@broadcom.com>
*
@ -13,8 +14,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Broadcom Vulcan";
compatible = "brcm,vulcan-soc";
model = "Cavium ThunderX2 CN99XX";
compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@ -26,28 +27,28 @@
cpu@0 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};

48
arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
View File

@ -94,27 +94,27 @@
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1075000>;
};
opp@267000000 {
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-microvolt = <1000000>;
};
opp@200000000 {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <975000>;
};
opp@160000000 {
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <962500>;
};
opp@134000000 {
opp-134000000 {
opp-hz = /bits/ 64 <134000000>;
opp-microvolt = <950000>;
};
opp@100000000 {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <937500>;
};
@ -123,19 +123,19 @@
bus_g2d_266_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp@267000000 {
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
};
opp@200000000 {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@160000000 {
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
};
opp@134000000 {
opp-134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};
@ -143,13 +143,13 @@
bus_gscl_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp@333000000 {
opp-333000000 {
opp-hz = /bits/ 64 <333000000>;
};
opp@222000000 {
opp-222000000 {
opp-hz = /bits/ 64 <222000000>;
};
opp@166500000 {
opp-166500000 {
opp-hz = /bits/ 64 <166500000>;
};
};
@ -158,22 +158,22 @@
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp@267000000 {
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
};
opp@200000000 {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@160000000 {
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
};
opp@134000000 {
opp-134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};
@ -181,16 +181,16 @@
bus_noc2_opp_table: opp_table6 {
compatible = "operating-points-v2";
opp@400000000 {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
opp@200000000 {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp@134000000 {
opp-134000000 {
opp-hz = /bits/ 64 <134000000>;
};
opp@100000000 {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
};

50
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -119,43 +119,43 @@
compatible = "operating-points-v2";
opp-shared;
opp@400000000 {
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
};
opp@500000000 {
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <925000>;
};
opp@600000000 {
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp@700000000 {
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <975000>;
};
opp@800000000 {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>;
};
opp@900000000 {
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1050000>;
};
opp@1000000000 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1075000>;
};
opp@1100000000 {
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1112500>;
};
opp@1200000000 {
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1112500>;
};
opp@1300000000 {
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1150000>;
};
@ -165,63 +165,63 @@
compatible = "operating-points-v2";
opp-shared;
opp@500000000 {
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <900000>;
};
opp@600000000 {
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
};
opp@700000000 {
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <912500>;
};
opp@800000000 {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <912500>;
};
opp@900000000 {
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <937500>;
};
opp@1000000000 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <975000>;
};
opp@1100000000 {
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
};
opp@1200000000 {
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
};
opp@1300000000 {
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
};
opp@1400000000 {
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1087500>;
};
opp@1500000000 {
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1125000>;
};
opp@1600000000 {
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1137500>;
};
opp@1700000000 {
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1175000>;
};
opp@1800000000 {
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1212500>;
};
opp@1900000000 {
opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1262500>;
};

4
arch/arm64/boot/dts/freescale/Makefile
View File

@ -5,9 +5,13 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

4
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
View File

@ -113,3 +113,7 @@
&sai2 {
status = "okay";
};
&sata {
status = "okay";
};

4
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View File

@ -126,3 +126,7 @@
&sai2 {
status = "okay";
};
&sata {
status = "okay";
};

4
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
View File

@ -57,3 +57,7 @@
&i2c0 {
status = "okay";
};
&sata {
status = "okay";
};

182
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -42,7 +42,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1012a";
@ -50,6 +51,15 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
crypto = &crypto;
rtic_a = &rtic_a;
rtic_b = &rtic_b;
rtic_c = &rtic_c;
rtic_d = &rtic_d;
sec_mon = &sec_mon;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -113,6 +123,95 @@
big-endian;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
};
rtic@60000 {
compatible = "fsl,sec-v5.4-rtic",
"fsl,sec-v5.0-rtic",
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x60000 0x100 0x60e00 0x18>;
ranges = <0x0 0x60100 0x500>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x100>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x100>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x100>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x400 0x100>;
};
};
};
sec_mon: sec_mon@1e90000 {
compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
"fsl,sec-v4.0-mon";
reg = <0x0 0x1e90000 0x0 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1012a-dcfg",
"syscon";
@ -127,6 +226,82 @@
clocks = <&sysclk>;
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration = <0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
big-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
@ -238,9 +413,12 @@
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 0>;
dma-coherent;
status = "disabled";
};
};

4
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -582,7 +582,9 @@
sata: sata@3200000 {
compatible = "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 0x4>;
clocks = <&clockgen 4 0>;
dma-coherent;

4
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -587,7 +587,9 @@
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};

123
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts Normal file
View File

@ -0,0 +1,123 @@
/*
* Device Tree file for NXP LS1088A QDS Board.
*
* Copyright 2017 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A QDS Board";
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};
&i2c0 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temp-sensor@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
/* IRQ10_B */
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
};
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
};
eeprom@57 {
compatible = "atmel,24c512";
reg = <0x57>;
};
};
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&sata {
status = "okay";
};

107
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts Normal file
View File

@ -0,0 +1,107 @@
/*
* Device Tree file for NXP LS1088A RDB Board.
*
* Copyright 2017 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
/ {
model = "L1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};
&i2c0 {
status = "okay";
i2c-switch@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temp-sensor@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
/* IRQ10_B */
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&sata {
status = "okay";
};

275
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi Normal file
View File

@ -0,0 +1,275 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
* Copyright 2017 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1088a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
/* We have 2 clusters having 4 Cortex-A53 cores each */
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clocks = <&clockgen 1 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clocks = <&clockgen 1 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clocks = <&clockgen 1 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clocks = <&clockgen 1 0>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
clocks = <&clockgen 1 1>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
clocks = <&clockgen 1 1>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
clocks = <&clockgen 1 1>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
clocks = <&clockgen 1 1>;
};
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1300000 {
compatible = "fsl,ls1088a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
status = "disabled";
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
};
};

155
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View File

@ -1,8 +1,9 @@
/*
* Device Tree file for Freescale LS2080a QDS Board.
*
* Copyright (C) 2015, Freescale Semiconductor
* Copyright (C) 2015-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
@ -47,6 +48,7 @@
/dts-v1/;
#include "fsl-ls2080a.dtsi"
#include "fsl-ls208xa-qds.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
@ -61,154 +63,3 @@
stdout-path = "serial0:115200n8";
};
};
&esdhc {
status = "okay";
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x5 0x80000000 0x08000000
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&dspi {
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <2>;
};
};
&qspi {
status = "okay";
flash0: s25fl256s1@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

110
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View File

@ -1,8 +1,9 @@
/*
* Device Tree file for Freescale LS2080a RDB Board.
*
* Copyright (C) 2015, Freescale Semiconductor
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
@ -47,6 +48,7 @@
/dts-v1/;
#include "fsl-ls2080a.dtsi"
#include "fsl-ls208xa-rdb.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
@ -61,109 +63,3 @@
stdout-path = "serial1:115200n8";
};
};
&esdhc {
status = "okay";
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x5 0x80000000 0x08000000
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};
};
&i2c0 {
status = "okay";
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&dspi {
status = "okay";
dflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
};
&qspi {
status = "disabled";
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

875
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -1,8 +1,9 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright (C) 2014-2015, Freescale Semiconductor
* Copyright (C) 2014-2016, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
@ -44,802 +45,122 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
#include "fsl-ls208xa.dtsi"
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
/*
* We expect the enable-method for cpu's to be "psci", but this
* is dependent on the SoC FW, which will fill this in.
*
* Currently supported enable-method is psci v0.2
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x301>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
&cpu {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
interrupts = <1 9 0x4>;
its: gic-its@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
rstcr: syscon@1e60000 {
compatible = "fsl,ls2080a-rstcr", "syscon";
reg = <0x0 0x1e60000 0x0 0x4>;
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
reboot {
compatible ="syscon-reboot";
regmap = <&rstcr>;
offset = <0x0>;
mask = <0x2>;
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 4>, /* Virtual PPI, active-low */
<1 10 4>; /* Hypervisor PPI, active-low */
fsl,erratum-a008585;
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x301>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dcfg: dcfg@1e00000 {
compatible = "fsl,ls2080a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>;
little-endian;
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration = <0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
little-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
trips {
cpu_alert: cpu-alert {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert>;
cooling-device =
<&cpu2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert>;
cooling-device =
<&cpu6 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
serial0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 0x4>; /* Level high type */
};
serial1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 0x4>; /* Level high type */
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
/*
* Define the maximum number of MACs present on the SoC.
*/
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
};
};
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
#global-interrupts = <12>;
interrupts = <0 13 4>, /* global secure fault */
<0 14 4>, /* combined secure interrupt */
<0 15 4>, /* global non-secure fault */
<0 16 4>, /* combined non-secure interrupt */
/* performance counter interrupts 0-7 */
<0 211 4>, <0 212 4>,
<0 213 4>, <0 214 4>,
<0 215 4>, <0 216 4>,
<0 217 4>, <0 218 4>,
/* per context interrupt, 64 interrupts */
<0 146 4>, <0 147 4>,
<0 148 4>, <0 149 4>,
<0 150 4>, <0 151 4>,
<0 152 4>, <0 153 4>,
<0 154 4>, <0 155 4>,
<0 156 4>, <0 157 4>,
<0 158 4>, <0 159 4>,
<0 160 4>, <0 161 4>,
<0 162 4>, <0 163 4>,
<0 164 4>, <0 165 4>,
<0 166 4>, <0 167 4>,
<0 168 4>, <0 169 4>,
<0 170 4>, <0 171 4>,
<0 172 4>, <0 173 4>,
<0 174 4>, <0 175 4>,
<0 176 4>, <0 177 4>,
<0 178 4>, <0 179 4>,
<0 180 4>, <0 181 4>,
<0 182 4>, <0 183 4>,
<0 184 4>, <0 185 4>,
<0 186 4>, <0 187 4>,
<0 188 4>, <0 189 4>,
<0 190 4>, <0 191 4>,
<0 192 4>, <0 193 4>,
<0 194 4>, <0 195 4>,
<0 196 4>, <0 197 4>,
<0 198 4>, <0 199 4>,
<0 200 4>, <0 201 4>,
<0 202 4>, <0 203 4>,
<0 204 4>, <0 205 4>,
<0 206 4>, <0 207 4>,
<0 208 4>, <0 209 4>;
mmu-masters = <&fsl_mc 0x300 0>;
};
dspi: dspi@2100000 {
status = "disabled";
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
clock-names = "dspi";
spi-num-chipselects = <5>;
bus-num = <0>;
};
esdhc: esdhc@2140000 {
status = "disabled";
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clock-frequency = <0>; /* Updated by bootloader */
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0: i2c@2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c1: i2c@2010000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c2: i2c@2020000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c3: i2c@2030000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 0x4>; /* Level high type */
little-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
};
qspi: quadspi@20c0000 {
status = "disabled";
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 25 0x4>; /* Level high type */
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "qspi_en", "qspi";
};
pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x10 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
<0000 0 0 2 &gic 0 0 0 110 4>,
<0000 0 0 3 &gic 0 0 0 111 4>,
<0000 0 0 4 &gic 0 0 0 112 4>;
};
pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x12 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
<0000 0 0 2 &gic 0 0 0 115 4>,
<0000 0 0 3 &gic 0 0 0 116 4>,
<0000 0 0 4 &gic 0 0 0 117 4>;
};
pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x14 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
<0000 0 0 2 &gic 0 0 0 120 4>,
<0000 0 0 3 &gic 0 0 0 121 4>,
<0000 0 0 4 &gic 0 0 0 122 4>;
};
pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x16 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 123 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
<0000 0 0 2 &gic 0 0 0 125 4>,
<0000 0 0 3 &gic 0 0 0 126 4>,
<0000 0 0 4 &gic 0 0 0 127 4>;
};
sata0: sata@3200000 {
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 133 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
dma-coherent;
};
sata1: sata@3210000 {
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3210000 0x0 0x10000>;
interrupts = <0 136 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
dma-coherent;
};
usb0: usb3@3100000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb3@3110000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
ccn@4000000 {
compatible = "arm,ccn-504";
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 17 0x4>;
little-endian;
cluster1_l2: l2-cache1 {
compatible = "cache";
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
interrupts = <0 18 0x4>;
little-endian;
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};
&pcie1 {
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x10 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie2 {
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x12 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie3 {
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x14 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie4 {
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x16 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

64
arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts Normal file
View File

@ -0,0 +1,64 @@
/*
* Device Tree file for Freescale LS2088A QDS Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls2088a.dtsi"
#include "fsl-ls208xa-qds.dtsi"
/ {
model = "Freescale Layerscape 2088A QDS Board";
compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

64
arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts Normal file
View File

@ -0,0 +1,64 @@
/*
* Device Tree file for Freescale LS2088A RDB Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "fsl-ls2088a.dtsi"
#include "fsl-ls208xa-rdb.dtsi"
/ {
model = "Freescale Layerscape 2088A RDB Board";
compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};

165
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi Normal file
View File

@ -0,0 +1,165 @@
/*
* Device Tree Include file for Freescale Layerscape-2088A family SoC.
*
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "fsl-ls208xa.dtsi"
&cpu {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x1>;
clocks = <&clockgen 1 0>;
next-level-cache = <&cluster0_l2>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
clocks = <&clockgen 1 1>;
next-level-cache = <&cluster1_l2>;
};
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>;
};
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x201>;
clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>;
};
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>;
};
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x301>;
clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
cluster2_l2: l2-cache2 {
compatible = "cache";
};
cluster3_l2: l2-cache3 {
compatible = "cache";
};
};
&pcie1 {
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x20 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
};
&pcie2 {
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x28 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
};
&pcie3 {
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x30 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
};
&pcie4 {
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x38 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
};

196
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi Normal file
View File

@ -0,0 +1,196 @@
/*
* Device Tree file for Freescale LS2080A QDS Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&esdhc {
status = "okay";
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x5 0x80000000 0x08000000
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&dspi {
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <2>;
};
};
&qspi {
status = "okay";
flash0: s25fl256s1@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
flash2: s25fl256s1@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

151
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi Normal file
View File

@ -0,0 +1,151 @@
/*
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright (C) 2016-17, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&esdhc {
status = "okay";
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0x5 0x80000000 0x08000000
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
reg = <0x2 0x0 0x10000>;
};
cpld@3,0 {
reg = <0x3 0x0 0x10000>;
compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
};
};
&i2c0 {
status = "okay";
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7481@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
&dspi {
status = "okay";
dflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
};
&qspi {
status = "disabled";
};
&sata0 {
status = "okay";
};
&sata1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

737
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi Normal file
View File

@ -0,0 +1,737 @@
/*
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright (C) 2016-2017, Freescale Semiconductor
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpu: cpus {
#address-cells = <1>;
#size-cells = <0>;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
interrupts = <1 9 0x4>;
its: gic-its@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;
};
};
rstcr: syscon@1e60000 {
compatible = "fsl,ls2080a-rstcr", "syscon";
reg = <0x0 0x1e60000 0x0 0x4>;
};
reboot {
compatible ="syscon-reboot";
regmap = <&rstcr>;
offset = <0x0>;
mask = <0x2>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 4>, /* Virtual PPI, active-low */
<1 10 4>; /* Hypervisor PPI, active-low */
fsl,erratum-a008585;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dcfg: dcfg@1e00000 {
compatible = "fsl,ls2080a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>;
little-endian;
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration = <0x00000000 0x00000026
0x00000001 0x0000002d
0x00000002 0x00000032
0x00000003 0x00000039
0x00000004 0x0000003f
0x00000005 0x00000046
0x00000006 0x0000004d
0x00000007 0x00000054
0x00000008 0x0000005a
0x00000009 0x00000061
0x0000000a 0x0000006a
0x0000000b 0x00000071
0x00010000 0x00000025
0x00010001 0x0000002c
0x00010002 0x00000035
0x00010003 0x0000003d
0x00010004 0x00000045
0x00010005 0x0000004e
0x00010006 0x00000057
0x00010007 0x00000061
0x00010008 0x0000006b
0x00010009 0x00000076
0x00020000 0x00000029
0x00020001 0x00000033
0x00020002 0x0000003d
0x00020003 0x00000049
0x00020004 0x00000056
0x00020005 0x00000061
0x00020006 0x0000006d
0x00030000 0x00000021
0x00030001 0x0000002a
0x00030002 0x0000003c
0x00030003 0x0000004e>;
little-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
trips {
cpu_alert: cpu-alert {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <85000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert>;
cooling-device =
<&cpu2 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_alert>;
cooling-device =
<&cpu4 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
map3 {
trip = <&cpu_alert>;
cooling-device =
<&cpu6 THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
};
};
};
};
serial0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 0x4>; /* Level high type */
};
serial1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 32 0x4>; /* Level high type */
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "apb_pclk", "wdog_clk";
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
msi-parent = <&its>;
#address-cells = <3>;
#size-cells = <1>;
/*
* Region type 0x0 - MC portals
* Region type 0x1 - QBMAN portals
*/
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
/*
* Define the maximum number of MACs present on the SoC.
*/
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
};
};
};
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
#global-interrupts = <12>;
interrupts = <0 13 4>, /* global secure fault */
<0 14 4>, /* combined secure interrupt */
<0 15 4>, /* global non-secure fault */
<0 16 4>, /* combined non-secure interrupt */
/* performance counter interrupts 0-7 */
<0 211 4>, <0 212 4>,
<0 213 4>, <0 214 4>,
<0 215 4>, <0 216 4>,
<0 217 4>, <0 218 4>,
/* per context interrupt, 64 interrupts */
<0 146 4>, <0 147 4>,
<0 148 4>, <0 149 4>,
<0 150 4>, <0 151 4>,
<0 152 4>, <0 153 4>,
<0 154 4>, <0 155 4>,
<0 156 4>, <0 157 4>,
<0 158 4>, <0 159 4>,
<0 160 4>, <0 161 4>,
<0 162 4>, <0 163 4>,
<0 164 4>, <0 165 4>,
<0 166 4>, <0 167 4>,
<0 168 4>, <0 169 4>,
<0 170 4>, <0 171 4>,
<0 172 4>, <0 173 4>,
<0 174 4>, <0 175 4>,
<0 176 4>, <0 177 4>,
<0 178 4>, <0 179 4>,
<0 180 4>, <0 181 4>,
<0 182 4>, <0 183 4>,
<0 184 4>, <0 185 4>,
<0 186 4>, <0 187 4>,
<0 188 4>, <0 189 4>,
<0 190 4>, <0 191 4>,
<0 192 4>, <0 193 4>,
<0 194 4>, <0 195 4>,
<0 196 4>, <0 197 4>,
<0 198 4>, <0 199 4>,
<0 200 4>, <0 201 4>,
<0 202 4>, <0 203 4>,
<0 204 4>, <0 205 4>,
<0 206 4>, <0 207 4>,
<0 208 4>, <0 209 4>;
mmu-masters = <&fsl_mc 0x300 0>;
};
dspi: dspi@2100000 {
status = "disabled";
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
clock-names = "dspi";
spi-num-chipselects = <5>;
bus-num = <0>;
};
esdhc: esdhc@2140000 {
status = "disabled";
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clock-frequency = <0>; /* Updated by bootloader */
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 0x4>; /* Level high type */
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0: i2c@2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c1: i2c@2010000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c2: i2c@2020000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
i2c3: i2c@2030000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
clock-names = "i2c";
clocks = <&clockgen 4 3>;
};
ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 0x4>; /* Level high type */
little-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x5 0x80000000 0x08000000
2 0 0x5 0x30000000 0x00010000
3 0 0x5 0x20000000 0x00010000>;
};
qspi: quadspi@20c0000 {
status = "disabled";
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <0 25 0x4>; /* Level high type */
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "qspi_en", "qspi";
};
pcie1: pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg-names = "regs", "config";
interrupts = <0 108 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
<0000 0 0 2 &gic 0 0 0 110 4>,
<0000 0 0 3 &gic 0 0 0 111 4>,
<0000 0 0 4 &gic 0 0 0 112 4>;
};
pcie2: pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg-names = "regs", "config";
interrupts = <0 113 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
<0000 0 0 2 &gic 0 0 0 115 4>,
<0000 0 0 3 &gic 0 0 0 116 4>,
<0000 0 0 4 &gic 0 0 0 117 4>;
};
pcie3: pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg-names = "regs", "config";
interrupts = <0 118 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
<0000 0 0 2 &gic 0 0 0 120 4>,
<0000 0 0 3 &gic 0 0 0 121 4>,
<0000 0 0 4 &gic 0 0 0 122 4>;
};
pcie4: pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
"snps,dw-pcie";
reg-names = "regs", "config";
interrupts = <0 123 0x4>; /* Level high type */
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
<0000 0 0 2 &gic 0 0 0 125 4>,
<0000 0 0 3 &gic 0 0 0 126 4>,
<0000 0 0 4 &gic 0 0 0 127 4>;
};
sata0: sata@3200000 {
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 133 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
dma-coherent;
};
sata1: sata@3210000 {
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3210000 0x0 0x10000>;
interrupts = <0 136 0x4>; /* Level high type */
clocks = <&clockgen 4 3>;
dma-coherent;
};
usb0: usb3@3100000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 80 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
usb1: usb3@3110000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
};
ccn@4000000 {
compatible = "arm,ccn-504";
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
};
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 17 0x4>;
little-endian;
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
interrupts = <0 18 0x4>;
little-endian;
};
};

1
arch/arm64/boot/dts/hisilicon/Makefile
View File

@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb

1
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View File

@ -8,6 +8,7 @@
/dts-v1/;
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
/ {
model = "HiKey960";

162
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts Normal file
View File

@ -0,0 +1,162 @@
/*
* DTS File for HiSilicon Poplar Development Board
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
/ {
model = "HiSilicon Poplar Development Board";
compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
aliases {
serial0 = &uart0;
serial2 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
user-led0 {
label = "USER-LED0";
gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
user-led1 {
label = "USER-LED1";
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
user-led2 {
label = "USER-LED2";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "off";
};
user-led3 {
label = "USER-LED3";
gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "cpu0";
default-state = "off";
};
};
};
&gmac1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&eth_phy1>;
phy-mode = "rgmii";
hisilicon,phy-reset-delays-us = <10000 10000 30000>;
eth_phy1: phy@3 {
reg = <3>;
};
};
&gpio1 {
status = "okay";
gpio-line-names = "LS-GPIO-E", "",
"", "",
"", "LS-GPIO-F",
"", "LS-GPIO-J";
};
&gpio2 {
status = "okay";
gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
"LS-GPIO-L", "LS-GPIO-G",
"LS-GPIO-K", "",
"", "";
};
&gpio3 {
status = "okay";
gpio-line-names = "", "",
"", "",
"LS-GPIO-C", "",
"", "LS-GPIO-B";
};
&gpio4 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "LS-GPIO-D",
"", "";
};
&gpio5 {
status = "okay";
gpio-line-names = "", "USER-LED-1",
"USER-LED-2", "",
"", "LS-GPIO-A",
"", "";
};
&gpio6 {
status = "okay";
gpio-line-names = "", "",
"", "USER-LED-0",
"", "",
"", "";
};
&gpio10 {
status = "okay";
gpio-line-names = "", "",
"", "",
"", "",
"USER-LED-3", "";
};
&i2c0 {
status = "okay";
label = "LS-I2C0";
};
&i2c2 {
status = "okay";
label = "LS-I2C1";
};
&ir {
status = "okay";
};
&spi0 {
status = "okay";
label = "LS-SPI0";
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
label = "LS-UART0";
};
/* No optional LS-UART1 on Low Speed Expansion Connector. */

411
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi Normal file
View File

@ -0,0 +1,411 @@
/*
* DTS File for HiSilicon Hi3798cv200 SoC.
*
* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
*
* Released under the GPLv2 only.
* SPDX-License-Identifier: GPL-2.0
*/
#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "hisilicon,hi3798cv200";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
<0x0 0xf1002000 0x0 0x100>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc@f0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xf0000000 0x10000000>;
crg: clock-reset-controller@8a22000 {
compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
reg = <0x8a22000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
gmacphyrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits =
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>,
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>;
};
};
sysctrl: system-controller@8000000 {
compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
reg = <0x8000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
uart0: serial@8b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: serial@8b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b02000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_UART2_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@8b10000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b10000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C0_CLK>;
status = "disabled";
};
i2c1: i2c@8b11000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b11000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C1_CLK>;
status = "disabled";
};
i2c2: i2c@8b12000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b12000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C2_CLK>;
status = "disabled";
};
i2c3: i2c@8b13000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b13000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C3_CLK>;
status = "disabled";
};
i2c4: i2c@8b14000 {
compatible = "hisilicon,hix5hd2-i2c";
reg = <0x8b14000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&crg HISTB_I2C4_CLK>;
status = "disabled";
};
spi0: spi@8b1a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8b1a000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
cs-gpios = <&gpio7 1 0>;
clocks = <&crg HISTB_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
emmc: mmc@9830000 {
compatible = "snps,dw-mshc";
reg = <0x9830000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_MMC_CIU_CLK>,
<&crg HISTB_MMC_BIU_CLK>;
clock-names = "ciu", "biu";
};
gpio0: gpio@8b20000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b20000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio1: gpio@8b21000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b21000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio2: gpio@8b22000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b22000 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio3: gpio@8b23000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b23000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio4: gpio@8b24000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b24000 0x1000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio5: gpio@8004000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8004000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio6: gpio@8b26000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b26000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio7: gpio@8b27000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b27000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio8: gpio@8b28000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b28000 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio9: gpio@8b29000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b29000 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio10: gpio@8b2a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2a000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio11: gpio@8b2b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2b000 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio12: gpio@8b2c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x8b2c000 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg HISTB_APB_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
gmac0: ethernet@9840000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9840000 0x1000>,
<0x984300c 0x4>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH0_MAC_CLK>,
<&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 8>,
<&crg 0xcc 10>,
<&gmacphyrst 0>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
gmac1: ethernet@9841000 {
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
reg = <0x9841000 0x1000>,
<0x9843010 0x4>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_ETH1_MAC_CLK>,
<&crg HISTB_ETH1_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 9>,
<&crg 0xcc 11>,
<&gmacphyrst 1>;
reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
ir: ir@8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0x8001000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_IR_CLK>;
status = "disabled";
};
};
};

3
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -774,6 +774,7 @@
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
reset-names = "reset";
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
pinctrl-names = "default";
@ -797,6 +798,7 @@
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
reset-names = "reset";
vqmmc-supply = <&ldo7>;
vmmc-supply = <&ldo10>;
bus-width = <0x4>;
@ -815,6 +817,7 @@
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
reset-names = "reset";
bus-width = <0x4>;
broken-cd;
pinctrl-names = "default", "idle";

407
arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi Normal file
View File

@ -0,0 +1,407 @@
/*
* pinctrl dts fils for Hislicon HiKey960 development board
*
*/
#include <dt-bindings/pinctrl/hisi.h>
/ {
soc {
/* [IOMG_000, IOMG_123] */
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
pmx0: pinmux@e896c000 {
compatible = "pinctrl-single";
reg = <0x0 0xe896c000 0x0 0x1f0>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <
&range 0 7 0
&range 8 116 0>;
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
0x064 MUX_M1 /* ISP_SCL0 */
0x068 MUX_M1 /* ISP_SDA0 */
>;
};
isp1_pmx_func: isp1_pmx_func {
pinctrl-single,pins = <
0x05c MUX_M1 /* ISP_CLK1 */
0x06c MUX_M1 /* ISP_SCL1 */
0x070 MUX_M1 /* ISP_SDA1 */
>;
};
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */
0x030 MUX_M1 /* I2C3_SDA */
>;
};
i2c4_pmx_func: i2c4_pmx_func {
pinctrl-single,pins = <
0x090 MUX_M1 /* I2C4_SCL */
0x094 MUX_M1 /* I2C4_SDA */
>;
};
pcie_perstn_pmx_func: pcie_perstn_pmx_func {
pinctrl-single,pins = <
0x15c MUX_M1 /* PCIE_PERST_N */
>;
};
usbhub5734_pmx_func: usbhub5734_pmx_func {
pinctrl-single,pins = <
0x11c MUX_M0 /* GPIO_073 */
0x120 MUX_M0 /* GPIO_074 */
>;
};
spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* SPI1_CLK */
0x038 MUX_M1 /* SPI1_DI */
0x03c MUX_M1 /* SPI1_DO */
0x040 MUX_M1 /* SPI1_CS_N */
>;
};
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */
0x0d4 MUX_M2 /* UART0_RXD_M */
0x0d8 MUX_M2 /* UART0_TXD_M */
>;
};
uart1_pmx_func: uart1_pmx_func {
pinctrl-single,pins = <
0x0b0 MUX_M2 /* UART1_CTS_N */
0x0b4 MUX_M2 /* UART1_RTS_N */
0x0a8 MUX_M2 /* UART1_RXD */
0x0ac MUX_M2 /* UART1_TXD */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0x0bc MUX_M2 /* UART2_CTS_N */
0x0c0 MUX_M2 /* UART2_RTS_N */
0x0c8 MUX_M2 /* UART2_RXD */
0x0c4 MUX_M2 /* UART2_TXD */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x0dc MUX_M1 /* UART3_CTS_N */
0x0e0 MUX_M1 /* UART3_RTS_N */
0x0e4 MUX_M1 /* UART3_RXD */
0x0e8 MUX_M1 /* UART3_TXD */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x0ec MUX_M1 /* UART4_CTS_N */
0x0f0 MUX_M1 /* UART4_RTS_N */
0x0f4 MUX_M1 /* UART4_RXD */
0x0f8 MUX_M1 /* UART4_TXD */
>;
};
uart5_pmx_func: uart5_pmx_func {
pinctrl-single,pins = <
0x0c4 MUX_M3 /* UART5_CTS_N */
0x0c8 MUX_M3 /* UART5_RTS_N */
0x0bc MUX_M3 /* UART5_RXD */
0x0c0 MUX_M3 /* UART5_TXD */
>;
};
uart6_pmx_func: uart6_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M1 /* UART6_CTS_N */
0x0d0 MUX_M1 /* UART6_RTS_N */
0x0d4 MUX_M1 /* UART6_RXD */
0x0d8 MUX_M1 /* UART6_TXD */
>;
};
};
/* [IOMG_MMC0_000, IOMG_MMC0_005] */
pmx1: pinmux@ff37e000 {
compatible = "pinctrl-single";
reg = <0x0 0xff37e000 0x0 0x18>;
#gpio-range-cells = <0x3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
sd_pmx_func: sd_pmx_func {
pinctrl-single,pins = <
0x000 MUX_M1 /* SD_CLK */
0x004 MUX_M1 /* SD_CMD */
0x008 MUX_M1 /* SD_DATA0 */
0x00c MUX_M1 /* SD_DATA1 */
0x010 MUX_M1 /* SD_DATA2 */
0x014 MUX_M1 /* SD_DATA3 */
>;
};
};
/* [IOMG_FIX_000, IOMG_FIX_011] */
pmx2: pinmux@ff3b6000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3b6000 0x0 0x30>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */
0x00c MUX_M1 /* SPI3_DI */
0x010 MUX_M1 /* SPI3_DO */
0x014 MUX_M1 /* SPI3_CS0_N */
>;
};
};
/* [IOMG_MMC1_000, IOMG_MMC1_005] */
pmx3: pinmux@ff3fd000 {
compatible = "pinctrl-single";
reg = <0x0 0xff3fd000 0x0 0x18>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 6 0>;
sdio_pmx_func: sdio_pmx_func {
pinctrl-single,pins = <
0x000 MUX_M1 /* SDIO_CLK */
0x004 MUX_M1 /* SDIO_CMD */
0x008 MUX_M1 /* SDIO_DATA0 */
0x00c MUX_M1 /* SDIO_DATA1 */
0x010 MUX_M1 /* SDIO_DATA2 */
0x014 MUX_M1 /* SDIO_DATA3 */
>;
};
};
/* [IOMG_AO_000, IOMG_AO_041] */
pmx4: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0xa8>;
#pinctrl-cells = <1>;
#gpio-range-cells = <0x3>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base in node, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 42 0>;
i2s2_pmx_func: i2s2_pmx_func {
pinctrl-single,pins = <
0x044 MUX_M1 /* I2S2_DI */
0x048 MUX_M1 /* I2S2_DO */
0x04c MUX_M1 /* I2S2_XCLK */
0x050 MUX_M1 /* I2S2_XFS */
>;
};
slimbus_pmx_func: slimbus_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* SLIMBUS_CLK */
0x030 MUX_M1 /* SLIMBUS_DATA */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0x014 MUX_M1 /* I2C0_SCL */
0x018 MUX_M1 /* I2C0_SDA */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0x01c MUX_M1 /* I2C1_SCL */
0x020 MUX_M1 /* I2C1_SDA */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0x024 MUX_M1 /* I2C2_SCL */
0x028 MUX_M1 /* I2C2_SDA */
>;
};
i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = <
0x024 MUX_M3 /* I2C7_SCL */
0x028 MUX_M3 /* I2C7_SDA */
>;
};
spi2_pmx_func: spi2_pmx_func {
pinctrl-single,pins = <
0x08c MUX_M1 /* SPI2_CLK */
0x090 MUX_M1 /* SPI2_DI */
0x094 MUX_M1 /* SPI2_DO */
0x098 MUX_M1 /* SPI2_CS0_N */
>;
};
spi4_pmx_func: spi4_pmx_func {
pinctrl-single,pins = <
0x08c MUX_M4 /* SPI4_CLK */
0x090 MUX_M4 /* SPI4_DI */
0x094 MUX_M4 /* SPI4_DO */
0x098 MUX_M4 /* SPI4_CS0_N */
>;
};
i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
0x038 MUX_M1 /* I2S0_DO */
0x03c MUX_M1 /* I2S0_XCLK */
0x040 MUX_M1 /* I2S0_XFS */
>;
};
};
pmx5: pinmux@ff3fd800 {
compatible = "pinconf-single";
reg = <0x0 0xff3fd800 0x0 0x18>;
#pinctrl-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
sdio_clk_cfg_func: sdio_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SDIO_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA
DRIVE6_MASK
>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SDIO_CMD */
0x008 0x0 /* SDIO_DATA0 */
0x00c 0x0 /* SDIO_DATA1 */
0x010 0x0 /* SDIO_DATA2 */
0x014 0x0 /* SDIO_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA
DRIVE6_MASK
>;
};
};
pmx6: pinmux@ff37e800 {
compatible = "pinconf-single";
reg = <0x0 0xff37e800 0x0 0x18>;
#pinctrl-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
sd_clk_cfg_func: sd_clk_cfg_func {
pinctrl-single,pins = <
0x000 0x0 /* SD_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_32MA
DRIVE6_MASK
>;
};
sd_cfg_func: sd_cfg_func {
pinctrl-single,pins = <
0x004 0x0 /* SD_CMD */
0x008 0x0 /* SD_DATA0 */
0x00c 0x0 /* SD_DATA1 */
0x010 0x0 /* SD_DATA2 */
0x014 0x0 /* SD_DATA3 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE6_19MA
DRIVE6_MASK
>;
};
};
};
};

20
arch/arm64/boot/dts/hisilicon/hip07-d05.dts
View File

@ -64,3 +64,23 @@
&usb_ehci {
status = "ok";
};
&eth0 {
status = "ok";
};
&eth1 {
status = "ok";
};
&eth2 {
status = "ok";
};
&eth3 {
status = "ok";
};
&sas1 {
status = "ok";
};

479
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@ -1014,6 +1014,34 @@
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xa0080000 0x0 0x10000>;
mbigen_pcie2_a: intc_pcie2_a {
msi-parent = <&p0_its_dsa_a 0x40087>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <10>;
};
mbigen_sas1: intc_sas1 {
msi-parent = <&p0_its_dsa_a 0x40000>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_sas2: intc_sas2 {
msi-parent = <&p0_its_dsa_a 0x40040>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_smmu_pcie: intc_smmu_pcie {
msi-parent = <&p0_its_dsa_a 0x40b0c>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
mbigen_usb: intc_usb {
msi-parent = <&p0_its_dsa_a 0x40080>;
interrupt-controller;
@ -1022,6 +1050,39 @@
};
};
p0_mbigen_dsa_a: interrupt-controller@c0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
mbigen_dsaf0: intc_dsaf0 {
msi-parent = <&p0_its_dsa_a 0x40800>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <409>;
};
mbigen_dsa_roce: intc-roce {
msi-parent = <&p0_its_dsa_a 0x40B1E>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <34>;
};
mbigen_sas0: intc-sas0 {
msi-parent = <&p0_its_dsa_a 0x40900>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_smmu_dsa: intc_smmu_dsa {
msi-parent = <&p0_its_dsa_a 0x40b20>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@ -1055,5 +1116,423 @@
dma-coherent;
status = "disabled";
};
peri_c_subctrl: sub_ctrl_c@60000000 {
compatible = "hisilicon,peri-subctrl","syscon";
reg = <0 0x60000000 0x0 0x10000>;
};
dsa_subctrl: dsa_subctrl@c0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0x0 0xc0000000 0x0 0x10000>;
};
pcie_subctl: pcie_subctl@a0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0x0 0xa0000000 0x0 0x10000>;
};
serdes_ctrl: sds_ctrl@c2200000 {
compatible = "syscon";
reg = <0 0xc2200000 0x0 0x80000>;
};
mdio@603c0000 {
compatible = "hisilicon,hns-mdio";
reg = <0x0 0x603c0000 0x0 0x1000>;
subctrl-vbase = <&peri_c_subctrl 0x338 0xa38
0x531c 0x5a1c>;
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
dsaf0: dsa@c7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
reset-field-offset = <0>;
interrupts =
<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
<1340 1>, <1341 1>, <1342 1>, <1343 1>;
desc-num = <0x400>;
buf-size = <0x1000>;
dma-coherent;
port@0 {
reg = <0>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <0>;
port-mode-offset = <0>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "fiber";
};
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "fiber";
};
port@4 {
reg = <4>;
phy-handle = <&phy0>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "copper";
};
port@5 {
reg = <5>;
phy-handle = <&phy1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
mc-mac-mask = [ff f0 00 00 00 00];
media-type = "copper";
};
};
eth0: ethernet@4{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet@5{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet@0{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet@1{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
infiniband@c4000000 {
compatible = "hisilicon,hns-roce-v1";
reg = <0x0 0xc4000000 0x0 0x100000>;
dma-coherent;
eth-handle = <&eth2 &eth3 0 0 &eth0 &eth1>;
dsaf-handle = <&dsaf0>;
node-guid = [00 9A CD 00 00 01 02 03];
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mbigen_dsa_roce>;
interrupts = <722 1>,
<723 1>,
<724 1>,
<725 1>,
<726 1>,
<727 1>,
<728 1>,
<729 1>,
<730 1>,
<731 1>,
<732 1>,
<733 1>,
<734 1>,
<735 1>,
<736 1>,
<737 1>,
<738 1>,
<739 1>,
<740 1>,
<741 1>,
<742 1>,
<743 1>,
<744 1>,
<745 1>,
<746 1>,
<747 1>,
<748 1>,
<749 1>,
<750 1>,
<751 1>,
<752 1>,
<753 1>,
<785 1>,
<754 4>;
interrupt-names = "hns-roce-comp-0",
"hns-roce-comp-1",
"hns-roce-comp-2",
"hns-roce-comp-3",
"hns-roce-comp-4",
"hns-roce-comp-5",
"hns-roce-comp-6",
"hns-roce-comp-7",
"hns-roce-comp-8",
"hns-roce-comp-9",
"hns-roce-comp-10",
"hns-roce-comp-11",
"hns-roce-comp-12",
"hns-roce-comp-13",
"hns-roce-comp-14",
"hns-roce-comp-15",
"hns-roce-comp-16",
"hns-roce-comp-17",
"hns-roce-comp-18",
"hns-roce-comp-19",
"hns-roce-comp-20",
"hns-roce-comp-21",
"hns-roce-comp-22",
"hns-roce-comp-23",
"hns-roce-comp-24",
"hns-roce-comp-25",
"hns-roce-comp-26",
"hns-roce-comp-27",
"hns-roce-comp-28",
"hns-roce-comp-29",
"hns-roce-comp-30",
"hns-roce-comp-31",
"hns-roce-async",
"hns-roce-common";
};
sas0: sas@c3000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xc3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&dsa_subctrl>;
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas0>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
<94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
<99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
<104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
<109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
<114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
<119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
<124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
<129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
<134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
<139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
<144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
<149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
<154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
<159 4>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
<610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
<615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
<620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
<625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
<630 1>,<631 1>,<632 1>;
status = "disabled";
};
sas1: sas@a2000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
hip06-sas-v2-quirk-amt;
ctrl-reset-reg = <0xa18>;
ctrl-reset-sts-reg = <0x5a0c>;
ctrl-clock-ena-reg = <0x318>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas1>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
<94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
<99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
<104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
<109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
<114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
<119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
<124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
<129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
<134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
<139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
<144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
<149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
<154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
<159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
<580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
<585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
<590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
<595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
<600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>;
status = "disabled";
};
sas2: sas@a3000000 {
compatible = "hisilicon,hip07-sas-v2";
reg = <0 0xa3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
ctrl-reset-reg = <0xae0>;
ctrl-reset-sts-reg = <0x5a70>;
ctrl-clock-ena-reg = <0x3a8>;
queue-count = <16>;
phy-count = <9>;
dma-coherent;
interrupt-parent = <&mbigen_sas2>;
interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
<197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
<202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
<207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
<212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
<217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
<222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
<227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
<232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
<237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
<242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
<247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
<252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
<257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
<262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
<267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
<272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
<277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
<282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
<287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
<612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
<617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
<622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
<627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
<632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
<637 1>,<638 1>,<639 1>;
status = "disabled";
};
};
};

50
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View File

@ -46,6 +46,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"
/ {
@ -60,10 +61,49 @@
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
exp_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&exp_usb3_vbus>;
};
};
&i2c0 {
status = "okay";
gpio_exp: pca9555@22 {
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x22>;
/*
* IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT
* IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE
* IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN
* IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN
* IO0_4: PWR_EN_SD
* IO0_5: PWR_EN_EMMC
* IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL
* IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS
*/
};
rtc@68 {
/* PT7C4337A from pericom fully compatible with the ds1337 */
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* CON3 */
@ -106,9 +146,19 @@
status = "okay";
};
&sdhci0 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,pad-type = "fixed-1-8v";
status = "okay";
};
/* CON31 */
&usb3 {
status = "okay";
usb-phy = <&usb3_phy>;
};
/* CON17 (PCIe) / CON12 (mini-PCIe) */

18
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -112,6 +112,8 @@
i2c0: i2c@11000 {
compatible = "marvell,armada-3700-i2c";
reg = <0x11000 0x24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&nb_periph_clk 10>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
mrvl,i2c-fast-mode;
@ -121,6 +123,8 @@
i2c1: i2c@11080 {
compatible = "marvell,armada-3700-i2c";
reg = <0x11080 0x24>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&nb_periph_clk 9>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
mrvl,i2c-fast-mode;
@ -196,7 +200,8 @@
compatible = "marvell,armada3700-xhci",
"generic-xhci";
reg = <0x58000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sb_periph_clk 12>;
status = "disabled";
};
@ -220,6 +225,17 @@
};
};
sdhci0: sdhci@d8000 {
compatible = "marvell,armada-3700-sdhci",
"marvell,sdhci-xenon";
reg = <0xd8000 0x300
0x17808 0x4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&nb_periph_clk 0>;
clock-names = "core";
status = "disabled";
};
sata: sata@e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;

43
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View File

@ -146,3 +146,46 @@
&cpm_usb3_1 {
status = "okay";
};
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};
&cpm_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};
&cpm_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpm_ethernet {
status = "okay";
};
&cpm_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
&cpm_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
&cpm_crypto {
status = "okay";
};

10
arch/arm64/boot/dts/marvell/armada-8020.dtsi
View File

@ -54,3 +54,13 @@
compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
"marvell,armada-ap806";
};
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
* in CP master is not connected (by package) to the oscillator. So
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
&cpm_rtc {
status = "disabled";
};

32
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View File

@ -124,6 +124,26 @@
status = "okay";
};
&cpm_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&cpm_ethernet {
status = "okay";
};
&cpm_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
&cpm_crypto {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
status = "okay";
@ -148,3 +168,15 @@
&cps_usb3_1 {
status = "okay";
};
&ap_sdhci0 {
status = "okay";
bus-width = <4>;
non-removable;
};
&cpm_sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
};

9
arch/arm64/boot/dts/marvell/armada-8040.dtsi
View File

@ -54,3 +54,12 @@
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
* in CP master is not connected (by package) to the oscillator. So
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
&cpm_rtc {
status = "disabled";
};

11
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -229,6 +229,17 @@
};
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&ap_syscon 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";

70
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View File

@ -59,6 +59,43 @@
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cpm_eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cpm_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
};
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@ -79,6 +116,13 @@
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
cpm_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
@ -173,6 +217,32 @@
clocks = <&cpm_syscon0 1 25>;
status = "okay";
};
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_syscon0 1 4>;
dma-coherent;
status = "disabled";
};
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_syscon0 1 26>;
status = "disabled";
};
};
cpm_pcie0: pcie@f2600000 {

60
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View File

@ -59,6 +59,50 @@
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cps_eth0: eth0 {
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cps_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
};
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@ -173,6 +217,22 @@
clocks = <&cps_syscon0 1 25>;
status = "okay";
};
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_syscon0 1 26>;
status = "disabled";
};
};
cps_pcie0: pcie@f4600000 {

2
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View File

@ -224,7 +224,7 @@
};
flow-controller@60007000 {
compatible = "nvidia,tegra124-flowctrl";
compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};

91
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@ -1,8 +1,99 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "tegra186-p3310.dtsi"
/ {
model = "NVIDIA Tegra186 P2771-0000 Development Board";
compatible = "nvidia,p2771-0000", "nvidia,tegra186";
i2c@3160000 {
power-monitor@42 {
compatible = "ti,ina3221";
reg = <0x42>;
};
power-monitor@43 {
compatible = "ti,ina3221";
reg = <0x43>;
};
exp1: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
exp2: gpio@77 {
compatible = "ti,tca9539";
reg = <0x77>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(Y, 6) GPIO_ACTIVE_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
};
/* SDMMC1 (SD/MMC) */
sdhci@3400000 {
status = "okay";
vmmc-supply = <&vdd_sd>;
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_POWER>;
debounce-interval = <10>;
wakeup-source;
};
volume-up {
label = "Volume Up";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2)
GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <10>;
};
};
regulators {
vdd_sd: regulator@100 {
compatible = "regulator-fixed";
reg = <100>;
regulator-name = "SD_CARD_SW_PWR";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
};
};

319
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@ -1,11 +1,23 @@
#include "tegra186.dtsi"
#include <dt-bindings/mfd/max77620.h>
/ {
model = "NVIDIA Tegra186 P3310 Processor Module";
compatible = "nvidia,p3310", "nvidia,tegra186";
aliases {
sdhci0 = "/sdhci@3460000";
sdhci1 = "/sdhci@3400000";
serial0 = &uarta;
i2c0 = "/bpmp/i2c";
i2c1 = "/i2c@3160000";
i2c2 = "/i2c@c240000";
i2c3 = "/i2c@3180000";
i2c4 = "/i2c@3190000";
i2c5 = "/i2c@31c0000";
i2c6 = "/i2c@c250000";
i2c7 = "/i2c@31e0000";
};
chosen {
@ -18,14 +30,99 @@
reg = <0x0 0x80000000 0x2 0x00000000>;
};
ethernet@2490000 {
status = "okay";
phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
phy-mode = "rgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
};
};
};
serial@3100000 {
status = "okay";
};
i2c@3160000 {
status = "okay";
power-monitor@40 {
compatible = "ti,ina3221";
reg = <0x40>;
};
power-monitor@41 {
compatible = "ti,ina3221";
reg = <0x41>;
};
};
i2c@3180000 {
status = "okay";
};
i2c@3190000 {
status = "okay";
};
i2c@31c0000 {
status = "okay";
};
i2c@31e0000 {
status = "okay";
};
/* SDMMC1 (SD/MMC) */
sdhci@3400000 {
cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vddio_sdmmc1>;
};
/* SDMMC3 (SDIO) */
sdhci@3440000 {
status = "okay";
};
/* SDMMC4 (eMMC) */
sdhci@3460000 {
status = "okay";
bus-width = <8>;
non-removable;
vqmmc-supply = <&vdd_1v8_ap>;
vmmc-supply = <&vdd_3v3_sys>;
};
hsp@3c00000 {
status = "okay";
};
i2c@c240000 {
status = "okay";
};
i2c@c250000 {
status = "okay";
};
pmc@c360000 {
nvidia,invert-interrupt;
};
cpus {
cpu@0 {
enable-method = "psci";
@ -53,7 +150,192 @@
};
bpmp {
status = "okay";
i2c {
status = "okay";
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
};
gpio1 {
pins = "gpio1";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
gpio2 {
pins = "gpio2";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
gpio3 {
pins = "gpio3";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
gpio4 {
pins = "gpio4";
function = "32k-out1";
drive-push-pull = <1>;
};
gpio5 {
pins = "gpio5";
function = "gpio";
drive-push-pull = <0>;
};
gpio6 {
pins = "gpio6";
function = "gpio";
drive-push-pull = <1>;
};
gpio7 {
pins = "gpio7";
function = "gpio";
drive-push-pull = <0>;
};
};
fps {
fps0 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
maxim,shutdown-fps-time-period-us = <640>;
};
fps1 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
maxim,shutdown-fps-time-period-us = <640>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
maxim,shutdown-fps-time-period-us = <640>;
};
};
regulators {
in-sd0-supply = <&vdd_5v0_sys>;
in-sd1-supply = <&vdd_5v0_sys>;
in-sd2-supply = <&vdd_5v0_sys>;
in-sd3-supply = <&vdd_5v0_sys>;
in-ldo0-1-supply = <&vdd_5v0_sys>;
in-ldo2-supply = <&vdd_5v0_sys>;
in-ldo3-5-supply = <&vdd_5v0_sys>;
in-ldo4-6-supply = <&vdd_1v8>;
in-ldo7-8-supply = <&avdd_dsi_csi>;
sd0 {
regulator-name = "VDD_DDR_1V1_PMIC";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
avdd_dsi_csi: sd1 {
regulator-name = "AVDD_DSI_CSI_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
vdd_1v8: sd2 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
vdd_3v3_sys: sd3 {
regulator-name = "VDD_3V3_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
ldo0 {
regulator-name = "VDD_1V8_AP_PLL";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "VDDIO_3V3_AOHV";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
vddio_sdmmc1: ldo3 {
regulator-name = "VDDIO_SDMMC1_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo4 {
regulator-name = "VDD_RTC";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vddio_sdmmc3: ldo5 {
regulator-name = "VDDIO_SDMMC3_AP";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
avdd_1v05: ldo7 {
regulator-name = "VDD_HDMI_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
vdd_pex: ldo8 {
regulator-name = "VDD_PEX_1V05";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
};
};
};
};
};
psci {
@ -61,4 +343,39 @@
status = "okay";
method = "smc";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_5v0_sys: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "VDD_5V0_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v8_ap: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "VDD_1V8_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* XXX */
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_1v8>;
};
};
};

59
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -2,6 +2,7 @@
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
/ {
@ -27,6 +28,37 @@
gpio-controller;
};
ethernet@2490000 {
compatible = "nvidia,tegra186-eqos",
"snps,dwc-qos-ethernet-4.10";
reg = <0x0 0x02490000 0x0 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
<&bpmp TEGRA186_CLK_EQOS_AXI>,
<&bpmp TEGRA186_CLK_EQOS_RX>,
<&bpmp TEGRA186_CLK_EQOS_TX>,
<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA186_RESET_EQOS>;
reset-names = "eqos";
status = "disabled";
snps,write-requests = <1>;
snps,read-requests = <3>;
snps,burst-map = <0x7>;
snps,txpbl = <32>;
snps,rxpbl = <8>;
};
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@ -307,6 +339,33 @@
#interrupt-cells = <2>;
};
pmc@c360000 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
};
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
<0x0 0x18000000 0x0 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
<&bpmp TEGRA186_CLK_GPU>;
clock-names = "gpu", "pwr";
resets = <&bpmp TEGRA186_RESET_GPU>;
reset-names = "gpu";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
};
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;

19
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@ -89,6 +89,8 @@
ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
iommus = <&mc TEGRA_SWGROUP_HC>;
dpaux1: dpaux@54040000 {
compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x54040000 0x0 0x00040000>;
@ -185,7 +187,14 @@
vic@54340000 {
compatible = "nvidia,tegra210-vic";
reg = <0x0 0x54340000 0x0 0x00040000>;
status = "disabled";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
clock-names = "vic";
resets = <&tegra_car 178>;
reset-names = "vic";
iommus = <&mc TEGRA_SWGROUP_VIC>;
power-domains = <&pd_vic>;
};
nvjpg@54380000 {
@ -755,6 +764,14 @@
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
#power-domain-cells = <0>;
};
pd_vic: vic {
clocks = <&tegra_car TEGRA210_CLK_VIC03>;
clock-names = "vic";
resets = <&tegra_car 178>;
reset-names = "vic";
#power-domain-cells = <0>;
};
};
};

11
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View File

@ -35,6 +35,17 @@
stdout-path = "serial0";
};
reserved-memory {
ramoops@bff00000{
compatible = "ramoops";
reg = <0x0 0xbff00000 0x0 0x100000>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x20000>;
};
};
soc {
dma@7884000 {
status = "okay";

26
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -157,7 +157,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
};
@ -833,8 +833,9 @@
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>;
clock-names = "iface", "bus", "mem";
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&xo_board>;
clock-names = "iface", "bus", "mem", "xo";
qcom,smem-states = <&hexagon_smp2p_out 0>;
qcom,smem-state-names = "stop";
@ -842,6 +843,7 @@
resets = <&scm 0>;
reset-names = "mss_restart";
cx-supply = <&pm8916_s1>;
mx-supply = <&pm8916_l3>;
pll-supply = <&pm8916_l7>;
@ -856,6 +858,16 @@
mpss {
memory-region = <&mpss_mem>;
};
smd-edge {
interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
qcom,ipc = <&apcs 8 12>;
qcom,remote-pid = <1>;
label = "hexagon";
};
};
pronto: wcnss@a21b000 {
@ -1214,14 +1226,6 @@
};
};
};
hexagon {
interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
qcom,ipc = <&apcs 8 12>;
qcom,remote-pid = <1>;
};
};
hexagon-smp2p {

Some files were not shown because too many files have changed in this diff Show More