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drm/i915: Add a mechanism for pipelining fence register updates
Not employed just yet... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Daniel Vetter
Chris Wilson
parent
caea7476d4
commit
c6642782b9
@ -2322,7 +2322,8 @@ i915_gpu_idle(struct drm_device *dev)
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return 0;
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}
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static void sandybridge_write_fence_reg(struct drm_i915_gem_object *obj)
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static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *pipelined)
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{
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struct drm_device *dev = obj->base.dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -2331,7 +2332,7 @@ static void sandybridge_write_fence_reg(struct drm_i915_gem_object *obj)
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uint64_t val;
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val = (uint64_t)((obj->gtt_offset + size - 4096) &
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0xfffff000) << 32;
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0xfffff000) << 32;
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val |= obj->gtt_offset & 0xfffff000;
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val |= (uint64_t)((obj->stride / 128) - 1) <<
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SANDYBRIDGE_FENCE_PITCH_SHIFT;
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@ -2340,10 +2341,26 @@ static void sandybridge_write_fence_reg(struct drm_i915_gem_object *obj)
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val |= 1 << I965_FENCE_TILING_Y_SHIFT;
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val |= I965_FENCE_REG_VALID;
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I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
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if (pipelined) {
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int ret = intel_ring_begin(pipelined, 6);
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if (ret)
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return ret;
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intel_ring_emit(pipelined, MI_NOOP);
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intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
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intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
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intel_ring_emit(pipelined, (u32)val);
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intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
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intel_ring_emit(pipelined, (u32)(val >> 32));
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intel_ring_advance(pipelined);
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} else
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I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
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return 0;
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}
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static void i965_write_fence_reg(struct drm_i915_gem_object *obj)
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static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *pipelined)
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{
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struct drm_device *dev = obj->base.dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -2359,27 +2376,41 @@ static void i965_write_fence_reg(struct drm_i915_gem_object *obj)
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val |= 1 << I965_FENCE_TILING_Y_SHIFT;
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val |= I965_FENCE_REG_VALID;
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I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
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if (pipelined) {
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int ret = intel_ring_begin(pipelined, 6);
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if (ret)
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return ret;
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intel_ring_emit(pipelined, MI_NOOP);
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intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
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intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
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intel_ring_emit(pipelined, (u32)val);
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intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
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intel_ring_emit(pipelined, (u32)(val >> 32));
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intel_ring_advance(pipelined);
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} else
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I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
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return 0;
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}
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static void i915_write_fence_reg(struct drm_i915_gem_object *obj)
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static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *pipelined)
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{
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struct drm_device *dev = obj->base.dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 size = obj->gtt_space->size;
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uint32_t fence_reg, val, pitch_val;
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u32 fence_reg, val, pitch_val;
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int tile_width;
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if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
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(obj->gtt_offset & (size - 1))) {
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WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
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__func__, obj->gtt_offset, obj->map_and_fenceable, size,
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obj->gtt_space->start, obj->gtt_space->size);
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return;
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}
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if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
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(size & -size) != size ||
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(obj->gtt_offset & (size - 1)),
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"object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
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obj->gtt_offset, obj->map_and_fenceable, size))
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return -EINVAL;
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if (obj->tiling_mode == I915_TILING_Y &&
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HAS_128_BYTE_Y_TILING(dev))
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if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
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tile_width = 128;
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else
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tile_width = 512;
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@ -2388,12 +2419,6 @@ static void i915_write_fence_reg(struct drm_i915_gem_object *obj)
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pitch_val = obj->stride / tile_width;
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pitch_val = ffs(pitch_val) - 1;
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if (obj->tiling_mode == I915_TILING_Y &&
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HAS_128_BYTE_Y_TILING(dev))
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WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
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else
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WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
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val = obj->gtt_offset;
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if (obj->tiling_mode == I915_TILING_Y)
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val |= 1 << I830_FENCE_TILING_Y_SHIFT;
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@ -2406,10 +2431,25 @@ static void i915_write_fence_reg(struct drm_i915_gem_object *obj)
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fence_reg = FENCE_REG_830_0 + fence_reg * 4;
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else
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fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
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I915_WRITE(fence_reg, val);
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if (pipelined) {
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int ret = intel_ring_begin(pipelined, 4);
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if (ret)
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return ret;
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intel_ring_emit(pipelined, MI_NOOP);
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intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(pipelined, fence_reg);
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intel_ring_emit(pipelined, val);
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intel_ring_advance(pipelined);
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} else
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I915_WRITE(fence_reg, val);
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return 0;
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}
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static void i830_write_fence_reg(struct drm_i915_gem_object *obj)
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static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *pipelined)
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{
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struct drm_device *dev = obj->base.dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -2417,29 +2457,38 @@ static void i830_write_fence_reg(struct drm_i915_gem_object *obj)
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int regnum = obj->fence_reg;
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uint32_t val;
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uint32_t pitch_val;
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uint32_t fence_size_bits;
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if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
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(obj->gtt_offset & (obj->base.size - 1))) {
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WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
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__func__, obj->gtt_offset);
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return;
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}
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if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
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(size & -size) != size ||
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(obj->gtt_offset & (size - 1)),
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"object 0x%08x not 512K or pot-size 0x%08x aligned\n",
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obj->gtt_offset, size))
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return -EINVAL;
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pitch_val = obj->stride / 128;
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pitch_val = ffs(pitch_val) - 1;
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WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
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val = obj->gtt_offset;
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if (obj->tiling_mode == I915_TILING_Y)
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val |= 1 << I830_FENCE_TILING_Y_SHIFT;
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fence_size_bits = I830_FENCE_SIZE_BITS(size);
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WARN_ON(fence_size_bits & ~0x00000f00);
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val |= fence_size_bits;
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val |= I830_FENCE_SIZE_BITS(size);
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val |= pitch_val << I830_FENCE_PITCH_SHIFT;
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val |= I830_FENCE_REG_VALID;
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I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
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if (pipelined) {
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int ret = intel_ring_begin(pipelined, 4);
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if (ret)
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return ret;
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intel_ring_emit(pipelined, MI_NOOP);
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intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
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intel_ring_emit(pipelined, val);
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intel_ring_advance(pipelined);
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} else
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I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
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return 0;
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}
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static int i915_find_fence_reg(struct drm_device *dev,
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@ -2512,6 +2561,7 @@ i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj,
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struct drm_device *dev = obj->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_fence_reg *reg = NULL;
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struct intel_ring_buffer *pipelined = NULL;
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int ret;
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/* Just update our place in the LRU if our fence is getting used. */
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@ -2553,25 +2603,24 @@ i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj,
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switch (INTEL_INFO(dev)->gen) {
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case 6:
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sandybridge_write_fence_reg(obj);
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ret = sandybridge_write_fence_reg(obj, pipelined);
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break;
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case 5:
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case 4:
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i965_write_fence_reg(obj);
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ret = i965_write_fence_reg(obj, pipelined);
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break;
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case 3:
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i915_write_fence_reg(obj);
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ret = i915_write_fence_reg(obj, pipelined);
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break;
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case 2:
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i830_write_fence_reg(obj);
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ret = i830_write_fence_reg(obj, pipelined);
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break;
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}
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trace_i915_gem_object_get_fence(obj,
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obj->fence_reg,
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obj->tiling_mode);
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return 0;
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return ret;
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}
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/**
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@ -164,7 +164,13 @@
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#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
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#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
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#define MI_STORE_DWORD_INDEX_SHIFT 2
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#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
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/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
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* - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
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* simply ignores the register load under certain conditions.
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* - One can actually load arbitrary many arbitrary registers: Simply issue x
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* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
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*/
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#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
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#define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */
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#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
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#define MI_BATCH_NON_SECURE (1)
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