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x86/mm: Make PGDIR_SHIFT and PTRS_PER_P4D variable
For boot-time switching between 4- and 5-level paging we need to be able to fold p4d page table level at runtime. It requires variable PGDIR_SHIFT and PTRS_PER_P4D. The change doesn't affect the kernel image size much: text data bss dec hex filename 8628091 4734304 1368064 14730459 e0c4db vmlinux.before 8628393 4734340 1368064 14730797 e0c62d vmlinux.after Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20180214111656.88514-7-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -48,6 +48,8 @@
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#ifdef CONFIG_X86_5LEVEL
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unsigned int pgtable_l5_enabled __ro_after_init = 1;
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unsigned int pgdir_shift __ro_after_init = 48;
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unsigned int ptrs_per_p4d __ro_after_init = 512;
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#endif
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extern unsigned long get_cmd_line_ptr(void);
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@ -33,6 +33,8 @@ static inline void pgtable_cache_init(void) { }
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static inline void check_pgt_cache(void) { }
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void paging_init(void);
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static inline int pgd_large(pgd_t pgd) { return 0; }
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/*
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* Define this if things work differently on an i386 and an i486:
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* it will (on an i486) warn about kernel memory accesses that are
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@ -26,6 +26,9 @@ extern unsigned int pgtable_l5_enabled;
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#define pgtable_l5_enabled 0
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#endif
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extern unsigned int pgdir_shift;
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extern unsigned int ptrs_per_p4d;
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#endif /* !__ASSEMBLY__ */
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#define SHARED_KERNEL_PMD 0
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@ -35,16 +38,17 @@ extern unsigned int pgtable_l5_enabled;
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT 48
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#define PGDIR_SHIFT pgdir_shift
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#define PTRS_PER_PGD 512
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/*
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* 4th level page in 5-level paging case
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*/
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#define P4D_SHIFT 39
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#define PTRS_PER_P4D 512
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#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
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#define P4D_MASK (~(P4D_SIZE - 1))
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#define P4D_SHIFT 39
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#define MAX_PTRS_PER_P4D 512
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#define PTRS_PER_P4D ptrs_per_p4d
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#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
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#define P4D_MASK (~(P4D_SIZE - 1))
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#define MAX_POSSIBLE_PHYSMEM_BITS 52
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@ -53,8 +57,9 @@ extern unsigned int pgtable_l5_enabled;
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/*
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* PGDIR_SHIFT determines what a top-level page table entry can map
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*/
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#define PGDIR_SHIFT 39
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#define PTRS_PER_PGD 512
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#define PGDIR_SHIFT 39
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#define PTRS_PER_PGD 512
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#define MAX_PTRS_PER_P4D 1
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#endif /* CONFIG_X86_5LEVEL */
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@ -1082,19 +1082,7 @@ void arch_unmap_kpfn(unsigned long pfn)
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* a legal address.
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*/
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/*
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* Build time check to see if we have a spare virtual bit. Don't want
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* to leave this until run time because most developers don't have a
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* system that can exercise this code path. This will only become a
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* problem if/when we move beyond 5-level page tables.
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*
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* Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD)
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*/
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#if PGDIR_SHIFT + 9 < 63
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decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
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#else
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#error "no unused virtual bit available"
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#endif
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if (set_memory_np(decoy_addr, 1))
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pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
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@ -2328,6 +2316,12 @@ static __init int mcheck_init_device(void)
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{
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int err;
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/*
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* Check if we have a spare virtual bit. This will only become
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* a problem if/when we move beyond 5-level page tables.
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*/
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MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
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if (!mce_available(&boot_cpu_data)) {
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err = -EIO;
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goto err_out;
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@ -42,6 +42,10 @@ pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
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#ifdef CONFIG_X86_5LEVEL
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unsigned int pgtable_l5_enabled __ro_after_init = 1;
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EXPORT_SYMBOL(pgtable_l5_enabled);
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unsigned int pgdir_shift __ro_after_init = 48;
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EXPORT_SYMBOL(pgdir_shift);
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unsigned int ptrs_per_p4d __ro_after_init = 512;
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EXPORT_SYMBOL(ptrs_per_p4d);
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#endif
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#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
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@ -336,7 +340,7 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data)
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BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0);
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BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0);
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BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
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BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
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MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
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(__START_KERNEL & PGDIR_MASK)));
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BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END);
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@ -428,14 +428,15 @@ static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr,
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#define p4d_none(a) pud_none(__pud(p4d_val(a)))
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#endif
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#if PTRS_PER_P4D > 1
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static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr, unsigned long P)
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{
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int i;
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p4d_t *start, *p4d_start;
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pgprotval_t prot;
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if (PTRS_PER_P4D == 1)
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return walk_pud_level(m, st, __p4d(pgd_val(addr)), P);
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p4d_start = start = (p4d_t *)pgd_page_vaddr(addr);
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for (i = 0; i < PTRS_PER_P4D; i++) {
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@ -455,11 +456,8 @@ static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr,
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}
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}
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#else
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#define walk_p4d_level(m,s,a,p) walk_pud_level(m,s,__p4d(pgd_val(a)),p)
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#define pgd_large(a) p4d_large(__p4d(pgd_val(a)))
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#define pgd_none(a) p4d_none(__p4d(pgd_val(a)))
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#endif
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#define pgd_large(a) (pgtable_l5_enabled ? pgd_large(a) : p4d_large(__p4d(pgd_val(a))))
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#define pgd_none(a) (pgtable_l5_enabled ? pgd_none(a) : p4d_none(__p4d(pgd_val(a))))
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static inline bool is_hypervisor_range(int idx)
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{
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@ -143,7 +143,7 @@ void sync_global_pgds(unsigned long start, unsigned long end)
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* With folded p4d, pgd_none() is always false, we need to
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* handle synchonization on p4d level.
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*/
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BUILD_BUG_ON(pgd_none(*pgd_ref));
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MAYBE_BUILD_BUG_ON(pgd_none(*pgd_ref));
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p4d_ref = p4d_offset(pgd_ref, addr);
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if (p4d_none(*p4d_ref))
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@ -19,7 +19,7 @@
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extern struct range pfn_mapped[E820_MAX_ENTRIES];
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static p4d_t tmp_p4d_table[PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE);
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static p4d_t tmp_p4d_table[MAX_PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE);
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static __init void *early_alloc(size_t size, int nid, bool panic)
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{
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@ -257,8 +257,8 @@ void efi_sync_low_kernel_mappings(void)
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* only span a single PGD entry and that the entry also maps
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* other important kernel regions.
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*/
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BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END));
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BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) !=
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MAYBE_BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END));
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MAYBE_BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) !=
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(EFI_VA_END & PGDIR_MASK));
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pgd_efi = efi_pgd + pgd_index(PAGE_OFFSET);
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@ -8,6 +8,7 @@
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#define P4D_SHIFT PGDIR_SHIFT
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#define P4D_SIZE PGDIR_SIZE
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#define P4D_MASK PGDIR_MASK
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#define MAX_PTRS_PER_P4D 1
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#define PTRS_PER_P4D 1
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#define p4d_t pgd_t
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typedef struct { pgd_t pgd; } p4d_t;
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#define P4D_SHIFT PGDIR_SHIFT
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#define PTRS_PER_P4D 1
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#define P4D_SIZE (1UL << P4D_SHIFT)
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#define P4D_MASK (~(P4D_SIZE-1))
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#define P4D_SHIFT PGDIR_SHIFT
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#define MAX_PTRS_PER_P4D 1
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#define PTRS_PER_P4D 1
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#define P4D_SIZE (1UL << P4D_SHIFT)
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#define P4D_MASK (~(P4D_SIZE-1))
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/*
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* The "pgd_xxx()" functions here are trivial for a folded two-level
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@ -18,7 +18,7 @@ extern unsigned char kasan_zero_page[PAGE_SIZE];
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extern pte_t kasan_zero_pte[PTRS_PER_PTE];
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extern pmd_t kasan_zero_pmd[PTRS_PER_PMD];
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extern pud_t kasan_zero_pud[PTRS_PER_PUD];
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extern p4d_t kasan_zero_p4d[PTRS_PER_P4D];
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extern p4d_t kasan_zero_p4d[MAX_PTRS_PER_P4D];
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void kasan_populate_zero_shadow(const void *shadow_start,
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const void *shadow_end);
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unsigned char kasan_zero_page[PAGE_SIZE] __page_aligned_bss;
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#if CONFIG_PGTABLE_LEVELS > 4
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p4d_t kasan_zero_p4d[PTRS_PER_P4D] __page_aligned_bss;
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p4d_t kasan_zero_p4d[MAX_PTRS_PER_P4D] __page_aligned_bss;
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#endif
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#if CONFIG_PGTABLE_LEVELS > 3
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pud_t kasan_zero_pud[PTRS_PER_PUD] __page_aligned_bss;
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