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drm/amdgpu: RAS EEPROM table is now in debugfs
Add "ras_eeprom_size" file in debugfs, which
reports the maximum size allocated to the RAS
table in EEROM, as the number of bytes and the
number of records it could store. For instance,
$cat /sys/kernel/debug/dri/0/ras/ras_eeprom_size
262144 bytes or 10921 records
$_
Add "ras_eeprom_table" file in debugfs, which
dumps the RAS table stored EEPROM, in a formatted
way. For instance,
$cat ras_eeprom_table
Signature Version FirstOffs Size Checksum
0x414D4452 0x00010000 0x00000014 0x000000EC 0x000000DA
Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage
0 0x00014 ue 0x00 0x00000000607608DC 0x000000000000 0x00 0x00 0x000000000000
1 0x0002C ue 0x00 0x00000000607608DC 0x000000001000 0x00 0x00 0x000000000001
2 0x00044 ue 0x00 0x00000000607608DC 0x000000002000 0x00 0x00 0x000000000002
3 0x0005C ue 0x00 0x00000000607608DC 0x000000003000 0x00 0x00 0x000000000003
4 0x00074 ue 0x00 0x00000000607608DC 0x000000004000 0x00 0x00 0x000000000004
5 0x0008C ue 0x00 0x00000000607608DC 0x000000005000 0x00 0x00 0x000000000005
6 0x000A4 ue 0x00 0x00000000607608DC 0x000000006000 0x00 0x00 0x000000000006
7 0x000BC ue 0x00 0x00000000607608DC 0x000000007000 0x00 0x00 0x000000000007
8 0x000D4 ue 0x00 0x00000000607608DD 0x000000008000 0x00 0x00 0x000000000008
$_
Cc: Alexander Deucher <Alexander.Deucher@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: John Clements <john.clements@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Xinhui Pan <xinhui.pan@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Luben Tuikov
Alex Deucher
parent
63d4c081a5
commit
c65b0805e7
@ -404,9 +404,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
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/* umc ce/ue error injection for a bad page is not allowed */
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if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
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amdgpu_ras_check_bad_page(adev, data.inject.address)) {
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dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
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"as bad before error injection!\n",
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data.inject.address);
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dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
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"already been marked as bad!\n",
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data.inject.address);
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break;
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}
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@ -1301,6 +1301,12 @@ static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *
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&con->bad_page_cnt_threshold);
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debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
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debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
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debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
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&amdgpu_ras_debugfs_eeprom_size_ops);
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con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
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S_IRUGO, dir, adev,
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&amdgpu_ras_debugfs_eeprom_table_ops);
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amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
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/*
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* After one uncorrectable error happens, usually GPU recovery will
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@ -318,6 +318,7 @@ struct amdgpu_ras {
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/* sysfs */
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struct device_attribute features_attr;
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struct bin_attribute badpages_attr;
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struct dentry *de_ras_eeprom_table;
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/* block array */
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struct ras_manager *objs;
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@ -27,6 +27,8 @@
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#include <linux/bits.h>
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#include "atom.h"
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#include "amdgpu_eeprom.h"
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#include <linux/debugfs.h>
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#include <linux/uaccess.h>
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#define EEPROM_I2C_MADDR_VEGA20 0x0
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#define EEPROM_I2C_MADDR_ARCTURUS 0x40000
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@ -70,6 +72,13 @@
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#define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
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(_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
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/* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
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* of "fri", return the absolute record index off of the end of
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* the table header.
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*/
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#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
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(_C)->ras_max_record_count)
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#define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
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RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
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@ -77,13 +86,10 @@
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static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
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{
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if ((adev->asic_type == CHIP_VEGA20) ||
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(adev->asic_type == CHIP_ARCTURUS) ||
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(adev->asic_type == CHIP_SIENNA_CICHLID) ||
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(adev->asic_type == CHIP_ALDEBARAN))
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return true;
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return false;
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return adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS ||
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adev->asic_type == CHIP_SIENNA_CICHLID ||
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adev->asic_type == CHIP_ALDEBARAN;
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}
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static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
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@ -258,6 +264,8 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
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control->ras_num_recs = 0;
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control->ras_fri = 0;
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amdgpu_ras_debugfs_set_ret_size(control);
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mutex_unlock(&control->ras_tbl_mutex);
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return res;
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@ -591,6 +599,8 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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res = amdgpu_ras_eeprom_append_table(control, record, num);
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if (!res)
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res = amdgpu_ras_eeprom_update_header(control);
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if (!res)
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amdgpu_ras_debugfs_set_ret_size(control);
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mutex_unlock(&control->ras_tbl_mutex);
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return res;
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@ -734,6 +744,223 @@ inline uint32_t amdgpu_ras_eeprom_max_record_count(void)
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return RAS_MAX_RECORD_COUNT;
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}
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static ssize_t
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amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
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u8 data[50];
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int res;
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if (!size)
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return size;
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if (!ras || !control) {
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res = snprintf(data, sizeof(data), "Not supported\n");
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} else {
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res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
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RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
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}
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if (*pos >= res)
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return 0;
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res -= *pos;
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res = min_t(size_t, res, size);
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if (copy_to_user(buf, &data[*pos], res))
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return -EINVAL;
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*pos += res;
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return res;
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}
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const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
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.owner = THIS_MODULE,
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.read = amdgpu_ras_debugfs_eeprom_size_read,
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.write = NULL,
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.llseek = default_llseek,
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};
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static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
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static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
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#define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
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static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
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static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
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#define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
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static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
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"ignore",
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"re",
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"ue",
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};
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static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
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{
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return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
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strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
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}
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void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
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{
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struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
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eeprom_control);
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struct dentry *de = ras->de_ras_eeprom_table;
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if (de)
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d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
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}
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static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
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const size_t orig_size = size;
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int res = -EINVAL;
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size_t data_len;
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mutex_lock(&control->ras_tbl_mutex);
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/* We want *pos - data_len > 0, which means there's
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* bytes to be printed from data.
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*/
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data_len = strlen(tbl_hdr_str);
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if (*pos < data_len) {
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data_len -= *pos;
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data_len = min_t(size_t, data_len, size);
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if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
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goto Out;
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buf += data_len;
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size -= data_len;
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*pos += data_len;
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}
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data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
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if (*pos < data_len && size > 0) {
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u8 data[tbl_hdr_fmt_size + 1];
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loff_t lpos;
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snprintf(data, sizeof(data), tbl_hdr_fmt,
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control->tbl_hdr.header,
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control->tbl_hdr.version,
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control->tbl_hdr.first_rec_offset,
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control->tbl_hdr.tbl_size,
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control->tbl_hdr.checksum);
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data_len -= *pos;
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data_len = min_t(size_t, data_len, size);
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lpos = *pos - strlen(tbl_hdr_str);
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if (copy_to_user(buf, &data[lpos], data_len))
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goto Out;
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buf += data_len;
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size -= data_len;
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*pos += data_len;
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}
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data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
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if (*pos < data_len && size > 0) {
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loff_t lpos;
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data_len -= *pos;
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data_len = min_t(size_t, data_len, size);
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lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
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if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
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goto Out;
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buf += data_len;
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size -= data_len;
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*pos += data_len;
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}
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data_len = amdgpu_ras_debugfs_table_size(control);
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if (*pos < data_len && size > 0) {
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u8 dare[RAS_TABLE_RECORD_SIZE];
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u8 data[rec_hdr_fmt_size + 1];
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/* Find the starting record index
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*/
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int s = (*pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
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strlen(rec_hdr_str)) / rec_hdr_fmt_size;
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int r = (*pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
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strlen(rec_hdr_str)) % rec_hdr_fmt_size;
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struct eeprom_table_record record;
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for ( ; size > 0 && s < control->ras_num_recs; s++) {
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u32 ai = RAS_RI_TO_AI(control, s);
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/* Read a single record
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*/
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res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
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if (res)
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goto Out;
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__decode_table_record_from_buf(control, &record, dare);
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snprintf(data, sizeof(data), rec_hdr_fmt,
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s,
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RAS_INDEX_TO_OFFSET(control, ai),
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record_err_type_str[record.err_type],
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record.bank,
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record.ts,
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record.offset,
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record.mem_channel,
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record.mcumc_id,
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record.retired_page);
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data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
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if (copy_to_user(buf, &data[r], data_len))
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return -EINVAL;
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buf += data_len;
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size -= data_len;
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*pos += data_len;
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r = 0;
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}
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}
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res = 0;
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Out:
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mutex_unlock(&control->ras_tbl_mutex);
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return res < 0 ? res : orig_size - size;
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}
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static ssize_t
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amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
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u8 data[81];
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int res;
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if (!size)
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return size;
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if (!ras || !control) {
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res = snprintf(data, sizeof(data), "Not supported\n");
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if (*pos >= res)
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return 0;
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res -= *pos;
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res = min_t(size_t, res, size);
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if (copy_to_user(buf, &data[*pos], res))
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return -EINVAL;
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*pos += res;
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return res;
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} else {
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return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
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}
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}
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const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
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.owner = THIS_MODULE,
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.read = amdgpu_ras_debugfs_eeprom_table_read,
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.write = NULL,
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.llseek = default_llseek,
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};
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/**
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* __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
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* @control: pointer to control structure
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@ -29,9 +29,10 @@
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struct amdgpu_device;
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enum amdgpu_ras_eeprom_err_type {
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AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
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AMDGPU_RAS_EEPROM_ERR_NA,
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AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
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AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
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AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE,
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AMDGPU_RAS_EEPROM_ERR_COUNT,
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};
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struct amdgpu_ras_eeprom_table_header {
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@ -121,4 +122,9 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
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inline uint32_t amdgpu_ras_eeprom_max_record_count(void);
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void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
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extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
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extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;
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#endif // _AMDGPU_RAS_EEPROM_H
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