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genirq: Fix various typos in comments
Go over the IRQ subsystem source code (including irqchip drivers) and fix common typos in comments. No change in functionality intended. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: linux-kernel@vger.kernel.org
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@ -105,7 +105,7 @@ static int __init dw_apb_ictl_init(struct device_node *np,
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* DW IP can be configured to allow 2-64 irqs. We can determine
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* the number of irqs supported by writing into enable register
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* and look for bits not set, as corresponding flip-flops will
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* have been removed by sythesis tool.
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* have been removed by synthesis tool.
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*/
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/* mask and enable all interrupts */
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@ -604,8 +604,8 @@ void gic_dist_save(struct gic_chip_data *gic)
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/*
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* Restores the GIC distributor registers during resume or when coming out of
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* idle. Must be called before enabling interrupts. If a level interrupt
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* that occured while the GIC was suspended is still present, it will be
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* handled normally, but any edge interrupts that occured will not be seen by
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* that occurred while the GIC was suspended is still present, it will be
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* handled normally, but any edge interrupts that occurred will not be seen by
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* the GIC and need to be handled by the platform-specific wakeup source.
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*/
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void gic_dist_restore(struct gic_chip_data *gic)
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@ -899,7 +899,7 @@ void gic_migrate_target(unsigned int new_cpu_id)
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gic_cpu_map[cpu] = 1 << new_cpu_id;
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/*
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* Find all the peripheral interrupts targetting the current
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* Find all the peripheral interrupts targeting the current
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* CPU interface and migrate them to the new CPU interface.
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* We skip DIST_TARGET 0 to 7 as they are read-only.
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*/
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* H8S interrupt contoller driver
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* H8S interrupt controller driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
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*/
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@ -58,7 +58,7 @@ struct s3c_irq_data {
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};
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/*
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* Sructure holding the controller data
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* Structure holding the controller data
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* @reg_pending register holding pending irqs
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* @reg_intpnd special register intpnd in main intc
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* @reg_mask mask register
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@ -19,7 +19,7 @@
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* the association between their DT compatible string and their
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* initialization function.
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*
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* @name: name that must be unique accross all IRQCHIP_DECLARE of the
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* @name: name that must be unique across all IRQCHIP_DECLARE of the
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* same file.
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* @compstr: compatible string of the irqchip driver
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* @fn: initialization function
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@ -30,7 +30,7 @@
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* This macro must be used by the different irqchip drivers to declare
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* the association between their version and their initialization function.
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*
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* @name: name that must be unique accross all IRQCHIP_ACPI_DECLARE of the
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* @name: name that must be unique across all IRQCHIP_ACPI_DECLARE of the
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* same file.
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* @subtable: Subtable to be identified in MADT
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* @validate: Function to be called on that subtable to check its validity.
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@ -929,7 +929,7 @@ __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
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break;
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/*
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* Bail out if the outer chip is not set up
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* and the interrrupt supposed to be started
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* and the interrupt supposed to be started
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* right away.
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*/
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if (WARN_ON(is_chained))
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@ -56,7 +56,7 @@ int irq_reserve_ipi(struct irq_domain *domain,
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unsigned int next;
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/*
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* The IPI requires a seperate HW irq on each CPU. We require
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* The IPI requires a separate HW irq on each CPU. We require
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* that the destination mask is consecutive. If an
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* implementation needs to support holes, it can reserve
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* several IPI ranges.
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@ -172,7 +172,7 @@ irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu)
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/*
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* Get the real hardware irq number if the underlying implementation
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* uses a seperate irq per cpu. If the underlying implementation uses
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* uses a separate irq per cpu. If the underlying implementation uses
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* a single hardware irq for all cpus then the IPI send mechanism
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* needs to take care of the cpu destinations.
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*/
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@ -915,7 +915,7 @@ irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { }
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#endif
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/*
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* Interrupts which are not explicitely requested as threaded
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* Interrupts which are not explicitly requested as threaded
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* interrupts rely on the implicit bh/preempt disable of the hard irq
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* context. So we need to disable bh here to avoid deadlocks and other
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* side effects.
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@ -66,7 +66,7 @@ static int try_one_irq(struct irq_desc *desc, bool force)
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raw_spin_lock(&desc->lock);
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/*
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* PER_CPU, nested thread interrupts and interrupts explicitely
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* PER_CPU, nested thread interrupts and interrupts explicitly
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* marked polled are excluded from polling.
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*/
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if (irq_settings_is_per_cpu(desc) ||
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@ -76,7 +76,7 @@ static int try_one_irq(struct irq_desc *desc, bool force)
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/*
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* Do not poll disabled interrupts unless the spurious
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* disabled poller asks explicitely.
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* disabled poller asks explicitly.
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*/
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if (irqd_irq_disabled(&desc->irq_data) && !force)
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goto out;
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@ -292,7 +292,7 @@ void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret)
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* So in case a thread is woken, we just note the fact and
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* defer the analysis to the next hardware interrupt.
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*
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* The threaded handlers store whether they sucessfully
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* The threaded handlers store whether they successfully
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* handled an interrupt and we check whether that number
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* changed versus the last invocation.
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*
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