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pmdomain: mediatek: Add support for MT8365
Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230918093751.1188668-9-msp@baylibre.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Fabien Parent
Ulf Hansson
parent
d2567a8452
commit
c5b5831f3c
197
drivers/pmdomain/mediatek/mt8365-pm-domains.h
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197
drivers/pmdomain/mediatek/mt8365-pm-domains.h
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@ -0,0 +1,197 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mediatek,mt8365-power.h>
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/*
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* MT8365 power domain support
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*/
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#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
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BUS_PROT_WR(INFRA, _mask, \
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MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
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MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
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MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
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#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
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BUS_PROT_WR(INFRA, _mask, \
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MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
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MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
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MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
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#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \
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BUS_PROT_WR(SMI, BIT(port), \
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MT8365_SMI_COMMON_CLAMP_EN_SET, \
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MT8365_SMI_COMMON_CLAMP_EN_CLR, \
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MT8365_SMI_COMMON_CLAMP_EN)
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#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \
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_BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \
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BUS_PROT_COMPONENT_INFRA | \
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BUS_PROT_STA_COMPONENT_INFRA_NAO | \
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BUS_PROT_INVERTED | \
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BUS_PROT_REG_UPDATE)
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static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
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[MT8365_POWER_DOMAIN_MM] = {
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.name = "mm",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = 0x30c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
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MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(
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MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
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MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
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MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
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MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
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MT8365_BUS_PROT_WAY_EN(
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MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
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MT8365_INFRA_TOPAXI_SI0_CTL,
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MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
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MT8365_INFRA_NAO_TOPAXI_SI0_STA),
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MT8365_BUS_PROT_WAY_EN(
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MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
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MT8365_INFRA_TOPAXI_SI2_CTL,
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MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
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MT8365_INFRA_NAO_TOPAXI_SI2_STA),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(
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MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
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},
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.caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
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},
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[MT8365_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = 0x0304,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
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},
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},
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[MT8365_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = 0x0314,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(12, 8),
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.sram_pdn_ack_bits = GENMASK(17, 13),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
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MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
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},
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8365_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = 0x032c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(
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MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(
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MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
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},
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.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8365_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = 0x0338,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
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MT8365_BUS_PROT_INFRA_WR_TOPAXI(
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MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
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MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
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},
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},
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[MT8365_POWER_DOMAIN_CAM] = {
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.name = "cam",
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.sta_mask = BIT(25),
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.ctl_offs = 0x0344,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
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MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
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},
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},
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[MT8365_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = BIT(31),
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.ctl_offs = 0x0370,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
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},
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},
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[MT8365_POWER_DOMAIN_APU] = {
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.name = "apu",
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.sta_mask = BIT(16),
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.ctl_offs = 0x0378,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(14, 8),
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.sram_pdn_ack_bits = GENMASK(21, 15),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
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MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
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MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
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},
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},
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[MT8365_POWER_DOMAIN_DSP] = {
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.name = "dsp",
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.sta_mask = BIT(17),
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.ctl_offs = 0x037C,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bp_cfg = {
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MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
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MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
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MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |
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MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
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},
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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};
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static const struct scpsys_soc_data mt8365_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8365,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),
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};
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#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */
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@ -24,6 +24,7 @@
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#include "mt8188-pm-domains.h"
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#include "mt8192-pm-domains.h"
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#include "mt8195-pm-domains.h"
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#include "mt8365-pm-domains.h"
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#define MTK_POLL_DELAY_US 10
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#define MTK_POLL_TIMEOUT USEC_PER_SEC
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@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] = {
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.compatible = "mediatek,mt8195-power-controller",
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.data = &mt8195_scpsys_data,
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},
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{
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.compatible = "mediatek,mt8365-power-controller",
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.data = &mt8365_scpsys_data,
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},
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{ }
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};
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@ -2,6 +2,47 @@
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
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#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
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#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
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#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
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#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
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#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
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#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
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#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
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#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
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#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
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#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
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#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
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#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
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#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
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#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
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#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
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