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drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode

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The execlist code already masks everything in the ring HWSTAM, but
the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6
platforms setup HWSTAM during irq setup already since there's just
the one register, and it also contains bits for non-ring interrupts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-13-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä 2017-08-18 21:37:01 +03:00
parent 3dcf4f207e
commit c549808946
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -428,6 +428,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = RING_HWS_PGA(engine->mmio_base);
}
if (INTEL_GEN(dev_priv) >= 6)
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
I915_WRITE(mmio, engine->status_page.ggtt_offset);
POSTING_READ(mmio);