From 9bef306b6ba250e20e49efb08a447d4bf95b7184 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Oct 2017 23:23:15 +0100 Subject: [PATCH 1/7] ARM: dts: meson8b: add more L2 cache settings Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 2048 sets, CACHE_ID 0x4100a0c9, Cache size: 524288 B AUX_CTRL 0x7ec60001, PERFETCH_CTRL 0x75000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Four differences still remain: - L310_AUX_CTRL_EARLY_BRESP is enabled by the vendor kernel, however this is only supported on Cortex-A9 cores (Meson8b has Cortex-A5 cores though) - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h - L310_AUX_CTRL_FULL_LINE_ZERO is enabled by the vendor kernel which is also only supported on Cortex-A9 cores Signed-off-by: Martin Blumenstingl Tested-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index d75e0ceda8bb..65e7d026f797 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -223,6 +223,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { From 6844e968b54977a1ad55cf8e80c6598369cacff8 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 31 Oct 2017 23:23:16 +0100 Subject: [PATCH 2/7] ARM: dts: meson8: add more L2 cache settings Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Two differences still remain: - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h Signed-off-by: Martin Blumenstingl Tested-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 2d7a0752a460..af3aa7058c5a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -308,6 +308,9 @@ arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; &pwm_ab { From b9b9db02018d5eddb06cf5e0fed9f70bd07b5900 Mon Sep 17 00:00:00 2001 From: Xingyu Chen Date: Thu, 16 Nov 2017 17:01:15 +0800 Subject: [PATCH 3/7] ARM: dts: meson: drop "sana" clock from SAR ADC The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan Tested-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- arch/arm/boot/dts/meson8b.dtsi | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index af3aa7058c5a..b962e11263e7 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -324,9 +324,8 @@ &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>; - clock-names = "clkin", "core", "sana"; + <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; }; &sdio { diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 65e7d026f797..b6de3edfcb21 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -239,9 +239,8 @@ &saradc { compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; clocks = <&clkc CLKID_XTAL>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>; - clock-names = "clkin", "core", "sana"; + <&clkc CLKID_SAR_ADC>; + clock-names = "clkin", "core"; }; &sdio { From 6ca77502050eff3aaa311e77b62b917219fe597d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 17 Nov 2017 23:58:56 +0100 Subject: [PATCH 4/7] ARM: dts: meson8: use stable UART bindings with correct gate clock Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b962e11263e7..8b4f5b367590 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -339,19 +339,27 @@ }; &uart_AO { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "baud", "xtal", "pclk"; }; &uart_A { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clock-names = "baud", "xtal", "pclk"; }; &uart_B { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clock-names = "baud", "xtal", "pclk"; }; &uart_C { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clock-names = "baud", "xtal", "pclk"; }; &usb0 { From b02d6e73f5fc96fcd71d50a62c764d4e2c500fa6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 17 Nov 2017 23:58:57 +0100 Subject: [PATCH 5/7] ARM: dts: meson8b: use stable UART bindings with correct gate clock Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index b6de3edfcb21..7cd03ed3742e 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -250,19 +250,27 @@ }; &uart_AO { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "baud", "xtal", "pclk"; }; &uart_A { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; + clock-names = "baud", "xtal", "pclk"; }; &uart_B { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; + clock-names = "baud", "xtal", "pclk"; }; &uart_C { - clocks = <&clkc CLKID_CLK81>; + compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; + clock-names = "baud", "xtal", "pclk"; }; &usb0 { From 59e45c691a7feab99df65201c4c7a4268383c48c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 30 Oct 2017 00:05:22 +0100 Subject: [PATCH 6/7] ARM: dts: meson8: enable the GPIO interrupt controller This enables the GPIO interrupt controller for the Meson8 SoCs. Interrupt support on the GPIOs can be used by the MMC framework to detect when an SD card is inserted/removed or by the input framework to detect button presses. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 8b4f5b367590..d2e3eeaa1a5f 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -286,6 +286,11 @@ clock-names = "stmmaceth"; }; +&gpio_intc { + compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; + status = "okay"; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; From 71a3dfd07ce1a69060bf040f28799171aa6a4ed3 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 30 Oct 2017 00:05:23 +0100 Subject: [PATCH 7/7] ARM: meson: enable MESON_IRQ_GPIO also for MACH_MESON8 Now that the GPIO interrupt controller also supports the Meson8 SoCs we can enable it via Kconfig. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/mach-meson/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index aff6164b2083..d90f61e6254f 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -23,6 +23,7 @@ config MACH_MESON8 default ARCH_MESON select MESON6_TIMER select COMMON_CLK_MESON8B + select MESON_IRQ_GPIO config MACH_MESON8B bool "Amlogic Meson8b SoCs support"